Data transfer between phase independent clock domains

Abstract

An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the arrangement comprising: a data transfer buffer for buffering a data stream for transfer between respective first and second ones of said regions, and a data transfer controller, associated with said data transfer buffer and said respective regions, configured to control transfer of said data stream by: initially synchronizing between said respective regions at a start of said data stream, receiving data, in said buffer, from said first region, at a predetermined rate, and outputting said data stream to said second region at said predetermined rate in accordance with said initial synchronization. The arrangement allows deterministic data patterns to arrive at the receiving domain at minimal hardware cost.

Description

FIELD AND BACKGROUND OF THE INVENTION[0001]The present invention relates to data transfer between phase independent clock domains and, more particularly, but not exclusively to a method or apparatus for deterministic data transfer between commonly clocked domains wherein an exact or variable phase difference is introduced by such factors as the circuit geometry.[0002]The trend today in silicon chip design is towards VLSI, and with larger and larger chips, smaller and smaller features and higher and higher clock rates, the result is that different regions on the chip can no longer be relied upon to be in time with a common clock. Even if the entire chip is commonly clocked, phase differences at different areas of the chip mean that interactions such as data transfer between one area and the other may require additional synchronization.[0003]More specifically, in the current art, the transfer of data between two logic sections located at relatively large distance from each other, typi...

AI Technical Summary

Problems solved by technology

The trend today in silicon chip design is towards VLSI, and with larger and larger chips, smaller and smaller features and higher and higher clock rates, the result is that different regions on the chip can no longer be relied upon to be in time with a common clock.

Even if the entire chip is commonly clocked, phase differences at different areas of the chip mean that interactions such as data transfer between one area and the other may require additional synchronization.

A disadvantage with the FIFO approach is that it results in a non-deterministic output data pattern.

The first two techniques may prove strenuous or impractical in some cases, while the third is hampered by the non-deterministic output data pattern.

A chip, or arrangement of chips, that does not produce a deterministic output pattern can be difficult to test.

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