Method and apparatus for correcting symbol timing
a technology of symbol timing and timing, applied in the field of method for correcting symbol timing, can solve problems such as inability to recover digital data correctly
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first embodiment
[0017]Please refer to FIG. 3. FIG. 3 shows a circuitry of the timing error detector 230 and the timing metric processing circuit 240 according to the present invention. In this embodiment, a timing error detector 310 includes quantizers 311 and 312. After timing error detector 310 processes the digital data D1, and timing metric M is generated. The timing metric M is transmitted to the timing metric processing circuit 240 and then a result M′ is generated. The result M′ is transmitted to the symbol timing correction circuit 250 for further processing. The timing error detector 310 utilizes the Mueller and Muller method architecture, and use T2 / 2 delay time for delaying the digital data D1 to get the correct symbol timing more effectively. On the other hands, based on the characteristic of the S-curve, the timing metric processing circuit 320 is modified to obtain more effective timing metrics compared to the timing metric processing circuit of prior art. The delay time of the delay ...
second embodiment
[0018]Please refer to FIG. 4. FIG. 4 shows a circuitry of the timing error detector 230 and the timing metric processing circuit 240 according to the present invention. In this embodiment, the timing error detector 310 is the same as the mention above, and the timing metric processing circuit 410 utilizes two delay circuits 412 and 414, the delay times of which are T2 and T2′. The periods of the delay times T2 and T2′ are the same, i.e., the periods of the two delay times can both be set T2, but the phase difference between the two delay times is T2 / 2. Allocated behind the delay circuit 414 is a multiplier 416, which multiplies every timing metric passing through the multiplier 416 by −1. That is, the sign of every timing metric M changes after the timing metric passes through the delay time 414. The delay times of delay circuits 412 and 414 are both T2, and the phase between them is set T2 / 2, i.e., a timing metric is effectively obtained every T2 / 2. Moreover, the sign of one of two...
third embodiment
[0019]Please refer FIG. 5. FIG. 5 shows a circuitry of the timing error detector 230 and the timing metric processing circuit 240 according to the present invention. In this embodiment, a timing error detector 510 includes quantizers 511 and 512. The timing error detector 510 also adopts the same Mueller and Muller method to generate timing metrics. The timing error detector 510 changes the sign in one of two successive timing metrics, summing one timing metric and the other sign-changed timing metric to generate a result, and then outputs the result. More specifically, the timing error detector 510 gets the two data D1[(k)T2 / 2] and D1[(k+2)T2 / 2] to generate a timing metric M1, and subsequently gets the two data D1[(k+1)T2 / 2] and D1 [(k+3)T2 / 2] to generate a timing metric M2. The timing error detector 510 changes the sign of the timing metric M2 and then adds the sign-changed M2 with M1, i.e., actually, the timing error detector 510 outputs a data of M1-M2 to the timing metric proce...
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