Nonvolatile semiconductor memory device for storing multivalued data
a semiconductor memory and multi-value technology, applied in static storage, digital storage, instruments, etc., can solve the problem of taking a long time to read data, and achieve the effect of shortening the data read time and reducing the number of operations
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first embodiment
[0050](First Embodiment)
[0051]The principle of a first embodiment of the present invention will be explained. FIGS. 1 and 2 show the relationship between the data in a memory cell and the threshold voltage of the memory cell. The data items in a memory cell, or state “0” to state “3”, are defined in ascending order, starting from the lowest threshold voltage of the memory cell. When erasing is done, the data in the memory cell goes to state “0”. A write operation causes the threshold voltage of the cell to move to a higher level.
[0052]As shown in FIGS. 1 and 2, in the memory cell according to the present invention, the data on the first and second pages corresponding to state “2” and state “3” differ from those in FIGS. 3 and 4. Specifically, when the data in the memory cell is in state “2”, the data on the first and second pages are set to “0”, “0”. When the data in the memory cell is in state “3”, the data on the first and second pages are set to “1”, “0”. When the data in the mem...
embodiment
[0067](Embodiment)
[0068]FIG. 8 schematically shows the configuration of a nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device is, for example, a NAND flash memory for storing four values (2 bits).
[0069]A memory cell array 1 includes bit lines, word lines, and common source lines. In the memory cell array 1, electrically rewritable memory cells composed of, for example, EEPROM cells are arranged in a matrix. A bit line control circuit 2 for controlling the bit lines and a word line control circuit 6 are connected to the memory cell array 1.
[0070]The bit line control circuit 2 includes data storage circuits as described later and read the data in a memory cell in the memory cell array 1 via a bit line or senses the state of a memory cell in the memory cell array 1 via a bit line. In addition, the bit line control circuit 2 applies a write control voltage to a memory cell in the memory cell array 1 via a bit line, ther...
second embodiment
[0091]An explanation of LAT(B1) and LAT(B2) will be given in the present invention.
[0092]The operation of the above configuration will be explained.
[0093]As described earlier, the data in the memory cell and the threshold voltage of the memory cell have been defined as shown in FIGS. 1 and 2. The data in the memory cell, or state “0” to state “3”, are defined in ascending order, starting from the lowest threshold voltage of the memory cell. In a memory cell, 2-bit data are stored. The 2-bit data are switched using a first-page address and a second-page address outside the nonvolatile semiconductor device.
[0094]With the states defined as described above, when the first-page address is specified in reading the data, if the data stored in the memory cell is in state “0” or state “3”, the data read out will be “1”.
[0095]If the data stored in the memory cell is in state “1” or state “2”, the data read out will be “0”. Therefore, the reading of the first page requires a total of two opera...
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