Method and device for guaranteeing reliable receiving syncronous data by tuning sampling clock

Abstract

Communication in synchronization mode is adopted between sending unit and receiving unit. Time interval between variation edge of data signal and sampling edge of sampling time signal of reaching the receiving unit is measured and analyzed. If the said time interval is less than build-up / holding time of the receiving unit, then processing of phase adjustment is carried out for the sampling time signal. The invention guarantees relation of time sequence between sampling time signal and data signal to meet requirement of receiving circuit. The invention suits any relation of time sequence between sending timing and sending data automatically, making the receiving unit receive data sent from the sending unit correctly. The above said function is realized by hardware. Thus, manually operation is not needed.

Description

technical field [0001] The present invention relates to a method and device for adjusting the sampling clock, in particular to a method for measuring and processing the sampling clock signal arriving at the receiving unit so that it has a timing relationship with the data signal suitable for reception by the receiving circuit The device and the device belong to the technical field of data communication. Background technique [0002] In the design of synchronous communication circuits, the sampling clock signal is generally used as the reference for sending and receiving data signals. Referring to Figure 1, the usual implementation method is: the sending unit 1 sends the data signal A with the rising edge (or falling edge) of the sampling clock signal B, and then sends the data signal A and the sampling clock signal B to the receiving unit 2 at the same time, and the receiving unit 2 The data signal A is sampled at the falling edge (or rising edge) of the sampling clock sign...

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Problems solved by technology

However, the disadvantage of this method is that if the sending unit 1 sends the data signal A on the rising edge, or the receiving unit 2 receives the data signal A on the falling edge, the circuit is connected with it, so that the sending unit 1 and the receiving unit 2 use the same The clock edge is used as a reference, it is difficult to meet the requirements in timing, and the reception is unreliable

However, the disadvantages of this approach are:

[0007] 1. The method of analyzing and judging whether there is a receiving error by the software is in the critical state (the critical state refers to: because the software cannot determine whether the setup / hold time of the receiving unit is sufficient, therefore, it may be that the setup / hold time is insufficient. The unit can still receive; but at this time, the change edge of the sampling clock signal is already in the boundary area, and it may not work reliably when the environment changes (such as temperature, voltage, current, etc.), which may lead to exceeding the boundary state and cause receiving errors), that is, it may This situation occurs: the normal reception work can be performed when the data signal is started to be received, and after a period of time, due to the accumulation of environmental changes to a corresponding extent, a reception error will occur, resulting in a temporary interruption of communication

[0008] 2. The receiving unit 2 is too dependent on the software, which will increase the difficulty of software design

[0009] 3. It is easily affected by interference factors. For example, the abnormal data signal sent by the sending unit 1 may cause the receiving unit 2 to mistake it for a timing problem

[0010] 4. Coupling effect is prone to occur, that is: when the judgment is wrong, the software may make a change to the sending unit 1 and the receiving unit 2 at the same time, and the result is: the sending unit 1 and the receiving unit 2 also use the same clock edge to work , still cannot meet the timing requirements

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