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Oversampling technique to reduce jitter

A digital signal, sampling interval technology, applied in the direction of synchronization device, digital transmission system, using signal quality detector for error detection/prevention, etc., can solve the problem of increasing sampling frequency, etc.

Inactive Publication Date: 2008-10-15
GVBB HLDG R L
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, increasing the sampling frequency will result in more samples
In some electronic systems, bandwidth constraints limit the number of samples that can be transmitted in a given interval
In such systems, there is limited opportunity for jitter performance improvement

Method used

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  • Oversampling technique to reduce jitter

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Embodiment Construction

[0012] FIG. 1 shows a prior art arrangement 10 for sampling an asynchronous digital signal 11 generated by a transmitter 12 . Transmitter 12 may take the form of any type of digital device that produces an asynchronous digital output signal. In other words, the output signal 11 of the transmitter 12 periodically changes state between a logic "1" level and a logic "0" level. The sampling device 10 includes a receiver 14 coupled to the output of the transmitter 12 for detecting the state of the signal in response to each pulse in a sequence of periodic clock pulses 15 from a sampling clock 16 . The sampling clock 16 generates m evenly spaced clock pulses 15 in an interval of duration t. In the illustrated embodiment, m=5, but the value of m can be larger or smaller.

[0013] The timing diagram of FIG. 2 shows the relationship in time between the output signal 11 of the transmitter 12 of FIG. 1 and the clock pulses 15 generated by the sampling clock 16 of FIG. 1 . In the examp...

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Abstract

The invention achieves improved jitter performance within prescribed bandwidth constraints, a receiver (140) samples a digital signal (11) upon each of n periodic sample clock pulses that occur during the interval t, where n is chosen such that log2(n+1) is an integer (x) greater than zero. At the each of each interval t, the receiver generates a x+1-bit sample value having a first bit indicating the value of the digital signal being sampled, and x remaining bits which collectively indicate a sample interval during which the digital signal changed states if such a change did occur When a change does occur, the receiver inverts the first bit of each sample value upon decoding to coincide with the change in the digital signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority under 35U.S.C. Priority of filed US Provisional Patent Application Serial No. 60 / 454,582, the teachings of both applications are incorporated herein. technical field [0003] The present invention relates to a technique for sampling an asynchronous digital signal to obtain reduced jitter performance. Background technique [0004] In various types of electronic systems, it is necessary to sample a digital signal to determine its state (ie, to determine whether the signal is at a logic "1" or logic "0" level). In practice, such sampling typically occurs periodically in response to periodic sampling clock pulses. Ideally, sampling should occur at a high enough frequency to minimize jitter, where jitter is generally defined as the uncertainty in the time between the change of state of the signal being sampled and the next sampling clock pulse. In the worst case, the signal being sampled ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M7/30H04L7/033H03M7/46H04L1/20H04L7/00H04L7/02
CPCH03M7/46H04L1/205H04L7/0331H04L7/0066H03M7/30H04L7/033
Inventor 罗伯特·阿伦·卡斯尔伯里罗伯特·劳埃德·舍曼
Owner GVBB HLDG R L
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