5+3 levels pipeline structure and method in RISC CPU

Abstract

This invention discloses one RISC CPU 5+3 water stream design structure and method, which changes traditional five degree water stream structure, which realizes single order circle to fulfill different types of order computations and adopts relative control mechanism to fulfill one CPU water stream control design with high property. This invention goes through different water stream degree according to different order.

Description

technical field [0001] The invention relates to a design method of a CPU pipeline, in particular to a design method of a pipeline in an embedded microprocessor. Background technique [0002] With the development of integrated circuit design and process technology, embedded systems (SOC) have been widely used in information terminals such as PDAs, set-top boxes, and mobile phones. He not only reduces the size of the circuit, but also has the advantages of low cost, high reliability, and low power consumption. It can be said that the embedded system is the direction of the development of integrated circuits in the future. As the core of the embedded system, the microprocessor is the indispensable "heart" of the SOC, and the performance of the microprocessor directly affects the performance of the entire SOC. The existing CPU architecture generally adopts the following forms: VLIW (Very Long Instruction Word Architecture), complex instruction set structure CISC (Complex Instr...

AI Technical Summary

Problems solved by technology

[0006] (1) Risks arise due to the simultaneous use of the same hardware resource by two execution units on the pipeline;

[0007] (2) Some instructions cannot complete the operation of the corresponding pipeline stage within one cycle, such as the multiplication instruction requires multiple cycles in the operation unit at the EX level;

[0009] (4) Instructions such as branch instructions, jump instructions, and abnormal returns cause changes in the program flow on the pipeline;

[0010] (5) Abnormalities may occur at any time during the execution of the pipeline

[0013] For the traditional CPU five-stage pipeline structure, if a special instruction occurs, at the last stage of the pipeline, all pipelines must stop and wait for the execution of the special instruction, and the response of other instructions will be suspended, and only after the special instruction is processed can it continue The operation of the pipeline will affect the processing speed of the CPU and reduce the efficiency.

In response to this phenomenon, some CPUs design the number of pipeline stages to be eight, but such processing changes the architecture of the CPU and increases hardware. Although other general instructions can also be processed at the same time when processing special instructions, but Most of the instructions are general instructions, that is, instructions that can be completed in five stages. Designing the number of stages of the CPU pipeline to eight stages not only wastes CPU processing time, but also increases hardware and increases costs.

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