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Network processing device and method

A technology of network processing and processing method, applied in the field of network processing units, can solve the problems of increasing the delay of interface data reaching the micro-engine, increasing the management complexity of storage units, reducing the performance of network processing units, etc. Effects of processing performance

Active Publication Date: 2009-01-21
XFUSION DIGITAL TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This will increase the management complexity of the storage unit (because there are multiple channels), and will also increase the delay for the interface data to reach the micro-engine, thereby reducing the performance of the network processing unit

Method used

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  • Network processing device and method
  • Network processing device and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] The address mapping settings of each stage are as shown image 3 As shown, the schematic diagram of its structure is shown in Figure 6 As shown, the network processing device 100 includes: an interface unit 101, a microengine unit 103, the interface unit includes a plurality of channels for receiving and forwarding messages; the microengine unit includes a plurality of microengines, The feature is that the device also includes: an address mapping unit 102, which is composed of a plurality of register segments, and is used for address mapping of segments; wherein, the messages in the channel are segmented according to the addresses of the address mapping unit Mappings are populated into the microengine's cache. Its specific mapping relationship is:

[0045] The n channel addresses of MAP Stage1 are all set to point to the address 0 of MAP Stage2, indicating that the n channels of the interface unit are valid, and messages may arrive in all of them. The 0 address of M...

Embodiment 2

[0050] The address mapping settings of each stage are as shown Figure 4 As shown, the schematic diagram of its structure is shown in Figure 6 As shown, the network processing device 100 includes: an interface unit 101, a microengine unit 103, the interface unit includes a plurality of channels for receiving and forwarding messages; the microengine unit includes a plurality of microengines, The feature is that the device also includes: an address mapping unit 102, which is composed of a plurality of register segments, and is used for address mapping of segments; wherein, the messages in the channel are segmented according to the addresses of the address mapping unit Mappings are populated into the microengine's cache. Its specific mapping relationship is:

[0051] The n channels of the MAP Stage1 address are all set to point to the value of the MAP Stage2 address, and the n channels of the MAP Stage1 address are all valid. The value set by channel 1 points to MAP Stage2 ad...

Embodiment 3

[0056] The address mapping settings of each stage are as shown Figure 5 As shown, the schematic diagram of its structure is shown in Figure 6 As shown, the network processing device 100 includes: an interface unit 101, a microengine unit 103, the interface unit includes a plurality of channels for receiving and forwarding messages; the microengine unit includes a plurality of microengines, The feature is that the device also includes: an address mapping unit 102, which is composed of a plurality of register segments, and is used for address mapping of segments; wherein, the messages in the channel are segmented according to the addresses of the address mapping unit Mappings are populated into the microengine's cache. Its specific mapping relationship is:

[0057]The two channel addresses of MAP Stage1 are set to point to MAP Stage2 address 0, the other two channel addresses of MAP Stage1 are set to point to MAP Stage2 address 3 and address 4 respectively, and the remaining...

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PUM

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Abstract

The network process device and method comprise: an interface unit with multiple channels to send and receive message, a micro-engine unit with multiple micro-engines, and an address mapping unit with lots registers for segmental address mapping. This invention fills the message into buffer on micro-engines according to mapping, and introduces convenience to software development.

Description

technical field [0001] The present invention relates to a network processing unit (NPU: Network Process Unit), specifically a network processing device and method. Background technique [0002] Network Processing Unit (NPU: Network Process Unit) is a programmable or configurable semiconductor device designed and optimized for processing network data (data packets). NPU optimizations include hardware and instruction sets to support high-speed packet classification and packet modification. The main function of the network processing unit is to offload the data transmission and processing tasks specific to network applications from the general-purpose processor, thereby greatly speeding up the processing and transmission of information packets. A network processing unit generally consists of a core processor (such as the Strong ARM core series) and multiple micro engines (Micro engines), which concurrently and synchronously complete the processing of a data packet. In the net...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/56G06F9/46H04L45/74
Inventor 易惕斌李君英余洲朱海培
Owner XFUSION DIGITAL TECH CO LTD
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