ESD protection circuit for enlarging the valid circulation area of the static current

A technology of circulation area and protective circuit, which is applied in the direction of circuits, electrical components, electric solid devices, etc., and can solve the problem that the effect of anti-static is not very ideal

Inactive Publication Date: 2009-03-18
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the anti-static effect of the thyristor SCR in the harsh static environment is not very ideal

Method used

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  • ESD protection circuit for enlarging the valid circulation area of the static current
  • ESD protection circuit for enlarging the valid circulation area of the static current
  • ESD protection circuit for enlarging the valid circulation area of the static current

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0021] Such as image 3 with Figure 4 As shown, the ESD protection circuit for increasing the effective flow area of ​​the electrostatic current includes a P-type substrate 31. The P-type substrate 31 is a well region. The well region includes an N-well 32 and a P-well 39. Both are provided with two injection regions, namely an N+ injection region 33 and a P+ injection region 35, and the two injection regions are isolated by a shallow trench isolation STI 34. The N+ injection region of the N well 32 is arranged at the end far away from the P well 39, the P+ injection area is arranged at the end close to the P well 39; the P+ injection area of ​​the P well 39 is arranged at the end far away from the N well 32, and the N+ injection area is arranged at Close to one end of the N-well 32; the central N+ implantation region 36 is arranged above the junction of the N-well 32 and the P-well 39 and bridges between the N-well 32 and the P-well 39. A polysilicon layer 37 is arranged above t...

Embodiment 2

[0023] Such as Figure 5 with Figure 6 As shown, the ESD protection circuit that increases the effective flow area of ​​the electrostatic current includes a P-type substrate 51. The P-type substrate 51 is a well region. The well region includes an N-well 52 and a P-well 59. Both are provided with two injection regions, namely the N+ injection region 53 and the P+ injection region 55, and the two injection regions are isolated by the shallow trench isolation STI 54. The N+ injection region of the N well 52 is arranged at the end far away from the P well 59, the P+ injection area is arranged at the end close to the P well 59; the P+ injection area of ​​the P well 59 is arranged at the end away from the N well 52, and the N+ injection area is arranged at Close to one end of the N-well 52; the central N+ implantation region 56 is disposed above the junction of the N-well 52 and the P-well 59 and bridges between the N-well 52 and the P-well 59. A polysilicon layer 57 is arranged above...

Embodiment 3

[0025] Such as Figure 7 with Figure 8 As shown, the ESD protection circuit that increases the effective flow area of ​​the electrostatic current includes a P-type substrate 71. The P-type substrate 71 is a well region. The well region includes an N-well 72 and a P-well 78. Both are provided with two injection areas, namely an N+ injection area 73 and a P+ injection area 74. The N+ injection region of the N well 72 is arranged at the end far away from the P well 78, the P+ injection area is arranged at the end close to the P well 78; the P+ injection area of ​​the P well 78 is arranged at the end away from the N well 72, and the N+ injection area is arranged at Close to one end of the N-well 72; the central N+ implantation region 75 is arranged above the junction of the N-well 72 and the P-well 78 and bridges between the N-well 72 and the P-well 78. A polysilicon layer 76 is arranged above the well region, and SiO is arranged between the polysilicon layer 76 and the well region 2 ...

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Abstract

The related static discharge protection circuit comprises: above the trap area, setting a multicrysta silicon layer and a SiO2 layer every with length not less than distance between the N-trap P+ injection area side wall near P-trap and the P-trap N+ injection area side wall near N-trap, and setting throughole on former two layers corresponding to the injection area. Unlike to current thyristor SCR method, this invention increases effective area for fast discharging, and improves the static tolerance capacity for the static discharge circuit.

Description

Technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an electrostatic discharge protection circuit that saves layout and increases the effective area of ​​electrostatic current discharge without changing the process. Background technique [0002] Electrostatic discharge is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating. The entire process takes about 100ns. In addition, a high voltage of hundreds or even thousands of volts will be generated when the integrated circuit is discharged, which will penetrate the gate oxide layer of the input stage in the integrated circuit. As the size of the MOS tube in the integrated circuit becomes smaller and smaller, the thickness of the gate oxide layer becomes thinner and thinner. Under this trend, a high-performance electrostatic protection circuit is used to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L23/60
Inventor 崔强韩雁董树荣霍明旭黄大海杜宇禅曾才赋洪慧陈茗杜晓阳斯瑞珺张吉皓
Owner ZHEJIANG UNIV
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