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A protection circuit for constructing ESD release channel with the polycrystalline silicon

A protection circuit and polysilicon technology, applied in the direction of circuits, electrical components, electric solid devices, etc., can solve the problems that the voltage value of the trigger point of the thyristor SCR cannot be adjusted flexibly, and the effect of anti-static is not very ideal.

Inactive Publication Date: 2009-03-18
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the anti-static effect of the thyristor SCR in a harsh electrostatic environment is not ideal, and the voltage value of the trigger point of the thyristor SCR cannot be adjusted flexibly

Method used

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  • A protection circuit for constructing ESD release channel with the polycrystalline silicon
  • A protection circuit for constructing ESD release channel with the polycrystalline silicon
  • A protection circuit for constructing ESD release channel with the polycrystalline silicon

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Embodiment Construction

[0015] The present invention will be further described in conjunction with the drawings and embodiments of the description.

[0016] like image 3 and Figure 4 As shown, a protection circuit using polysilicon to construct an ESD discharge channel includes a P-type substrate 30 on which is a well region, and the well region includes an N well 31 and a P well 39 . Both the N well 31 and the P well 39 are provided with two implanted regions, which are N+ implanted region 32 a and P+ implanted region 34 . Wherein the N+ implantation region 32a of the N well 31 is arranged on one end away from the P well 39, and the P+ implantation region 34 is arranged on one end close to the P well 39; Region 32a is disposed near one end of N well 31; N+ implant region 32a and P+ implant region 34 on N well 31 and P well 39 are isolated by shallow trench isolation STI 33a. A polysilicon layer is disposed between the P+ implantation region 34 of the N well 31 and the N+ implantation region 32a...

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Abstract

The related static discharge protection circuit comprises: based on current SCR, setting a multicrysta silicon layer and a SiO2 layer between the last layer and trap area, a P+ and N+ multicrystal injection area on sides of the silicon layer, and an intrinsic multicrystal silicon area on midst. This invention sets throughole on two layers and STI on trap area corresponding to the throughhole, arranges a N+ injection area in the STI, equal to the parallel connection of a P-I-N or N-I-P mutlicrystal silicon and a SCR, improves protection capacity, and convenient to adjust the trigger voltage of this protection circuit.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an electrostatic discharge protection circuit using polysilicon layout layers to construct electrostatic current discharge channels. Background technique [0002] Electrostatic discharge is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating, and the whole process takes about 100ns. In addition, hundreds or even thousands of volts of high voltage will be generated when the integrated circuit is discharged, which will break through the gate oxide layer of the input stage in the integrated circuit. As the size of MOS transistors in integrated circuits is getting smaller and smaller, the thickness of the gate oxide layer is also getting thinner. Under this trend, high-performance electrostatic protection circuits are used to discharge electrostat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L23/60
Inventor 韩雁崔强董树荣霍明旭黄大海杜宇禅曾才赋洪慧陈茗杜晓阳斯瑞珺张吉皓
Owner ZHEJIANG UNIV