Calibration of up and down charge-pump currents using a sample-and-hold circuit during idle times

A technology of charge pump and sampling transistor, which is applied in the direction of electrical components, automatic control of power, and conversion equipment without intermediate conversion to AC, etc.

Inactive Publication Date: 2009-04-29
PERICOM TECH (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This delay and distortion will also cause an additional difference

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  • Calibration of up and down charge-pump currents using a sample-and-hold circuit during idle times
  • Calibration of up and down charge-pump currents using a sample-and-hold circuit during idle times
  • Calibration of up and down charge-pump currents using a sample-and-hold circuit during idle times

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Embodiment Construction

[0051] The present invention is an improvement over charge pumps. The following description will describe the context of the details of this patent application and its essential requirements. Many improvements and related theories will be discussed in detail. Therefore, the present invention will not intentionally limit the detailed and specific description, but will detail the relevant principles and present novel features in a wide range.

[0052] The inventor realized that the charge pump has better charge matching by using the sample-and-hold technique. The charge pump consists of a current source and a current sink. Current flows from a current source and is forced all through a current discharge transistor. The discharge transistor has its gate and source connected together, operates in saturation, and has a current proportional to the square of the gate-to-source voltage above its threshold voltage. The gate-source voltage is adjusted to sink a current equal to that...

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Abstract

A charge pump for a phase-locked loop (PLL) has accurate matching of charge and discharge currents applied to the PLL's loop filter. A variable current-sink transistor has its gate-to-source voltage adjusted to match a source current from a fixed current source. An intermediate node in-between series transistors between the current source and sink is sampled by a sampling transistor that connects the intermediate node to a sampling capacitor. The sampling capacitor's voltage is the gate-to-source voltage of the variable current-sink transistor. The variable current-sink transistor has its gate and drain coupled together through the sampling transistor during calibration periods when the charge pump is otherwise idle. When the source current exactly matches the sink current, the gate-to-source voltage stored on the sampling capacitor reaches steady state. Up and down currents are balanced in driver transistors that match the series transistors.

Description

technical field [0001] The present invention is related to phase-locked loop (PLL) charge pump technology, and in particular to sample-and-hold charge pumps. Background technique [0002] Digital systems often rely on precise clocks and data transfers synchronized with the timing of operations. Crystal oscillators are often used to generate a base frequency clock, which can then be divided or multiplied to generate one or more frequencies depending on the desired frequency. An external clock can be used as an internal clock after frequency division or multiplication. Usually the clock is generated from the oscillator output by using a phase-locked loop (hereinafter referred to as PLL). A PLL is a unit circuit widely used in today's digital systems. [0003] figure 1 Shown is a typical PLL. Phase detector 10 receives a reference clock from an external oscillator or clock source. The phase and frequency of the reference clock are compared with the feedback clock generate...

Claims

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Application Information

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IPC IPC(8): H02M3/07H03L7/06H03L7/16
CPCH03L7/0896
Inventor张善銮黄永基
OwnerPERICOM TECH (SHANGHAI) CO LTD