Method for simultaneously loading multiple FPGA using CPU

Abstract

The invention discloses a method for simultaneously loading multiple FPGAs with a CPU, which is used for a system including a single or multiple FPGAs and a CPU, and is characterized in that it includes: Step 1, by loading bitstream files of multiple FPGAs Merging processing generates an FPGA loading file; Step 2, the address bus of the CPU is logically expanded to obtain the required registers and latches for loading the multiple FPGAs; and Step 3, the CPU reads the FPGA loading The file is sent to the extended memory of the CPU, and the loading sequence is generated by controlling the register and the latch to load the multiple FPGAs or one FPGA in the multiple FPGAs. Compared with the prior art, the method of the invention greatly accelerates the loading speed of the CPU to multiple FPGAs, improves the reliability and flexibility of the loading circuit, and effectively saves the capacity of the external FLASH.

Description

technical field [0001] The present invention relates to the loading technology of FPGA (Field Programmable Gate Array, Field Programmable Gate Array) with CPU, particularly relate to in the system of multi-chip FPGA, and under the situation that system has certain requirement for loading speed, use CPU to simultaneously load multiple A method for fast loading of FPGA. Background technique [0002] Usually, two methods are used to load FPGA with CPU. One is to connect multiple FPGAs with a daisy chain and download them serially. The disadvantage of this method is that when the FPGA scale is large, it may take a few minutes to If a certain FPGA in the daisy chain cannot be loaded due to a fault, it may cause all FPGAs on the daisy chain to fail to load, and storing the download files of multiple FPGAs in advance will occupy a large FLASH storage space; another The method is to download each FPGA as an independent individual in turn, but it also has the disadvantages of long d...

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide a method for simultaneously loading multiple FPGAs with a CPU, which is used to solve the problem of long loading time, large load program occupation space, and large FPGA loading problems in the prior art when the CPU loads multiple FPGAs. When the problem occurs, it will affect the entire loading time and even affect the loading of other FPGAs, and the traditional way of loading FPGAs will occupy a large number of CPU I / O ports.

Images