Stack type semiconductor packaging structure

Abstract

A stackable semiconductor package structure is provided, which comprises a first substrate, a semiconductor element, a second substrate, a plurality of first lead wires, a support adhesive member and a first packaging adhesive. The semiconductor element is positioned on the first substrate. The second substrate is positioned above the semiconductor element and has an area larger than the semiconductor element. The first lead wire is electrically connected with the second substrate and the first substrate. The support adhesive member is positioned between the first substrate and the second substrate, to support the second substrate. The first packaging adhesive exposes a part of solder pads of the second substrate. Therefore, during the wire bonding operation, the suspension part of the second substrate doesn't swing and vibrate, and the area of the second substrate can be increased to store more elements. Additionally, the thickness of the second substrate can be reduced to reduce the total thickness of the stackable semiconductor package structure.

Description

technical field [0001] The invention relates to a stackable semiconductor package structure, in particular to a stackable semiconductor package structure with supporting colloid. Background technique [0002] Please refer to figure 1 , showing a schematic cross-sectional view of a conventional stackable semiconductor package structure. The conventional stackable semiconductor package structure 1 includes a first substrate 11 , a chip 12 , a second substrate 13 , a plurality of wires 14 and a sealing material 15 . The first substrate 11 has a first surface 111 and a second surface 112 . The chip 12 is attached to the first surface 111 of the first substrate 11 in a flip-chip manner. The second substrate 13 is adhered on the chip 12 by an adhesive layer 16. The second substrate 13 has a first surface 131 and a second surface 132, wherein the first surface 131 has a plurality of first pads 133 and a plurality of second solder pads. Pad 134. The area of ​​the second substra...

AI Technical Summary

Problems solved by technology

First of all, since the second substrate 13 will have a suspended part, the first pad 133 is located at the periphery of the relative position of the chip 12 (ie the suspended part), and the distance between the first solder pad 133 and the relative position of the edge of the chip 12 is defined as the suspended part. The length L1. Experiments show that when the suspended length L1 is more than three times greater than the thickness T1 of the second substrate 13, the suspended part will shake or vibrate during the wire bonding operation, which is not conducive to carrying out Wire work

What's more, when the second substrate 13 receives too much downward stress during the wire bonding operation, it will cause the second substrate 13 to crack.

Secondly, due to the above-mentioned shaking, vibration or cracking, the suspended part should not be too long, so that the area of ​​the second substrate 13 is limited, so that the first surface 131 of the second substrate 13 exposed by the sealing opening 17 is limited. The layout space on the second pad 134

Finally, in order to reduce the above shaking, vibration or cracking, the thickness of the second substrate 13 should not be too thin, so the overall thickness of the existing stackable semiconductor package structure 1 cannot be effectively reduced.

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