Semiconductor device and method for manufacturing the same

Abstract

After forming the groove (36) that exposes the semiconductor substrate (31), remove a part of the semiconductor layer (51, 52) respectively disposed under the semiconductor layer (33, 35), and form the end of the semiconductor layer (33, 35). The gaps (60a, 60b) exposed from the semiconductor layers (51, 52) on the upper and lower surfaces of the upper and lower parts respectively pass through the sidewalls of the conductor layers (33, 35) to detour to the lower side of the semiconductor layers (33, 35) to support The body (56) is embedded in the groove (36, 37), a cavity (57a) is formed between the semiconductor substrate (31) and the semiconductor layer (33), and a cavity (57a) is formed between the semiconductor layers (33, 35). 57b) After that, an embedded insulating layer (39) embedded in the cavity (57a, 57b) is formed. Thereby, the performance of threshold value control by the back gate electrode can be improved, and the parasitic capacitance with the source / drain layer can be reduced.

Description

technical field [0001] The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device, in particular to a manufacturing method applicable to a method for forming a field effect transistor provided with a back gate electrode. Background technique [0002] Since field effect transistors formed on SOI substrates have the characteristics of easy separation of elements, free latch up, and small source / drain junction capacitance, their usefulness has attracted much attention. In particular, since fully depleted SOI transistors can realize low power consumption, high-speed operation, and easy low-voltage driving, researches on making SOI transistors operate in fully depleted mode have been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxygen) substrate, an adhesive substrate, or the like is used. [0003] Furthermore, in conventional semiconduct...

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Problems solved by technology

[0011] However, in conventional semiconductor integrated circuits, if the channel length is shortened along with the miniaturization of transistors, the rise characteristics of the drain current in the subthreshold region will deteriorate.

Therefore, there is a problem that the low-voltage operation of the transistor is hindered, and the leakage current at the off-time increases, not only the power consumption during the operation and the standby time increases, but also the main cause of the destruction of the transistor.

[0012] In addition, if the back gate electrode is arranged on the entire surface under the field effect transistor, the parasitic capacitance between the back gate electrode and the source / drain layer increases, which will cause a problem that hinders the speed-up of the SOI transistor.

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