Semiconductor device and method for manufacturing the same

Abstract

After the grooves 36 exposing the semiconductor substrate 31 is formed, a part of each of the semiconductor layers 51 and 52 respectively arranged under the semiconductor layers 33 and 35 is removed. This allows formation of spaces 60a and 60b for exposing top and bottom surfaces of ends of the semiconductor layers 33 and 35, respectively, from the semiconductor layers 51 and 52, the support member 56 can be buried in the grooves 36 and 37 and reach under the semiconductor layers 33 and 35 via sidewalls of the semiconductor layers 33 and 35, a space 57a is formed between the semiconductor substrate 31 and the semiconductor layer 33 and also a space 57b is formed between the semiconductor layers 33 and 35, a buried insulating layer 39 is formed so as to be buried in the spaces 57a and 57b. Accordingly, the present invention is capable of improving threshold controllability by using a backgate electrode and reducing parasitic capacitance between the backgate electrode and source and drain layers.

Description

technical field [0001] The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device, in particular to a manufacturing method applicable to a method for forming a field effect transistor provided with a back gate electrode. Background technique [0002] Since field effect transistors formed on SOI substrates have the characteristics of easy separation of elements, free latch up, and small source / drain junction capacitance, their usefulness has attracted much attention. In particular, since fully depleted SOI transistors can realize low power consumption, high-speed operation, and easy low-voltage driving, researches on making SOI transistors operate in fully depleted mode have been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxygen) substrate, an adhesive substrate, or the like is used. [0003] Furthermore, in conventional semiconduct...

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Problems solved by technology

[0011] However, in conventional semiconductor integrated circuits, if the channel length is shortened along with the miniaturization of transistors, the rise characteristics of the drain current in the subthreshold region will deteriorate.

Therefore, there is a problem that the low-voltage operation of the transistor is hindered, and the leakage current at the off-time increases, not only the power consumption during the operation and the standby time increases, but also the main cause of the destruction of the transistor.

[0012] In addition, if the back gate electrode is arranged on the entire surface under the field effect transistor, the parasitic capacitance between the back gate electrode and the source / drain layer increases, which will cause a problem that hinders the speed-up of the SOI transistor.

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