Producing method of micro link lug structure with stress buffer
A technology of stress buffering and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., and can solve the problems that high-end packaging chips cannot bear longitudinal and lateral stresses, etc.
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[0054] see figure 1 As shown, it is the first implementation structure diagram of the micro-connected bump with stress buffering of the present invention, wherein the bump includes a first top surface 11, and the first top surface 11 is connected to one of the substrate and the electronic component, wherein Electronic components generally refer to general chips (Chip) or other integrated circuits (IC) using surface bonding technology (SMT). A second top surface 12, the second top surface 12 is connected to one of the substrate and the electronic component, of course, the electronic component also refers to a chip or an integrated circuit; a support body 13 is connected to the first top surface 11 and the second top surface Between the surfaces 12, and the surface area of the two ends of the support body 13 is not larger than the first top surface 11 and the second top surface 12, and this embodiment is a columnar body. The connection structure of the first top surface 11, t...
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