Semiconductor assembly, seal ring structure and forming method thereof

Abstract

A seal ring structure between an integrated circuit region and a scribe line is provided. In one embodiment, the seal ring structure comprises a substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; a first passivation layer formed over the plurality of layers of metal lines, the first passivation layer having an opening therein exposing a portion of a top metal line; residual metal pad layers formed proximal the opening of the first passivation layer; and a second passivation layer formed over the first passivation layer, the second passivation layer enveloping the exposed residual metal pad or metal redistribution layers and further having a trench above the top metal line.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit, more particularly to a sealing ring structure, which is used to reduce the stress generated when cutting chips. Background technique [0002] In semiconductor manufacturing methods, areas on a wafer are divided into chips with integrated circuits, and dicing streets that separate the chips. Cutting along the dicing lines separates the entire wafer into dies. [0003] However, the lateral stress generated during the cutting process will affect the structure of the integrated circuit, and the generated microcracks will eventually reduce the process efficiency. The solution is to form a sealing ring structure between the dicing line and the periphery of the integrated circuit. The known sealing ring structure is a metal connection connected by a line-type via. FIG. 1 is a top view of a conventional sealing ring structure surrounding a certain chip before wafer dicing. The scribe line...

AI Technical Summary

Problems solved by technology

In addition, the process of forming bumps or other IC patterns before dicing the wafer, such as chemical etching, will make the residual aluminum pad 140 useless.

The remaining aluminum pads cause serious negative effects such as short circuit and parasitic capacitance in the fabricated components, or become conductive channels between IC patterns (such as bumps) to short circuit

Images