Testing method capable of configuring FPGA configurable logic block with five times

Abstract

A method for testing FPGA configurable logic blocks that has been configured five times, and is characterized in that it combines sequential logic circuits and combinational logic circuits of FPGA configurable logic blocks for testing, arranges test resources optimally, and cross-uses NOR and XOR The test vectors of equal functions and exhaustive method reduce the number of test configurations; the technology of cascading serpentine one-dimensional arrays is used in the present invention, and all the configurable logic blocks to be tested are arranged according to satisfying test controllability and test observability It is required to test in series, which not only simplifies the design complexity, but also reduces the test input and output ports, and achieves 100% test coverage, effectively reducing the test cost.

Description

technical field [0001] The invention relates to a test method of an FPGA chip, in particular to a test method for completing FPGA configurable logic blocks with only five configurations. Background technique [0002] The premise of testing the FPGA is to configure it, design a variety of test circuits and go through multiple configuration-test processes to achieve effective testing of the FPGA. It takes much more time to configure an FPGA than to apply a test vector, so the key to improving the efficiency of FPGA testing is to minimize the number of configurations while ensuring test coverage. [0003] The configurable logic block is the most basic functional unit in the FPGA, and the comprehensive test of the configurable logic block is in a very important position in the FPGA testing technology. At present, foreign countries have conducted research on the testing of FPGA configurable logic blocks, and proposed the theory that the configurable logic blocks are divided into...

AI Technical Summary

Problems solved by technology

[0004] The problem solved by the present invention is to reduce the number of configurations as much as possible, and provide a method for testing FPGA configurable logic blocks through five configurations. It guarantees the requirements of test controllability and test observability, and overcomes the shortcomings of many test configurations, complex test circuit structure and low efficiency in the past

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