Bit line pre-charging producer of dynamic RAM

Abstract

The present invention provides a DRAM bit line precharge voltage generator, which includes: a first amplifier having a first current source and comparing the first voltage with the precharge voltage to control a first PMOS transistor; a second amplifier having a first Two current sources and compare the second voltage with the precharge voltage to control the second PMOS transistor, a third amplifier with a third current source and compare the third voltage with the precharge voltage to control the first NMOS transistor, and a fourth An amplifier having a fourth current source and comparing the first voltage with the precharge voltage to control a second NMOS transistor. The precharge voltage is fed back from an output node connected between the second PMOS transistor and the first NMOS transistor.

Description

technical field [0001] The present invention relates to a dynamic random access memory (DRAM) bit line precharge voltage generator, and more particularly, to a DRAM bit line precharge voltage generator using feedback of its output signal. Background technique [0002] DRAM requires a highly stable bit line precharge voltage to meet the demand for long refresh cycles, therefore, the bit line precharge voltage generator must exhibit the characteristics of easy stability and low output impedance. In general, when a DRAM bit line precharge voltage generator applies a precharge voltage to a bit line of a semiconductor device, the precharge voltage has a value corresponding to half of the supply voltage, (V cc -V ss ) / 2(reference figure 1 ). [0003] In US Patent No. 5,255,232 (hereinafter '232), a DRAM bit line precharge voltage generator is disclosed. figure 1 A circuit diagram of DRAM precharge voltage generator 1 in '232 is shown. The precharge voltage generator 1 include...

AI Technical Summary

Problems solved by technology

However, for low density DRAMs (e.g., capacities below 16 Mb), current process technology produces some failure modes that result in leakage currents in the bit lines

In order to compensate the leakage current in low-density DRAM, the MOS transistor used in the voltage adjustment circuit 2 must be designed with high driving capability (ie, large size), or with a small equivalent RC value providing a high-frequency pole , however such a designed MOS transistor will easily lead to instability of the voltage regulation circuit 2

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