Method for dynamically allocating memory of computer system
A technology of computer system and dynamic memory, which is applied in the direction of memory system, calculation, memory address/allocation/relocation, etc., and can solve time-consuming and high-cost problems
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[0036] FIG. 1 illustrates key parts of a set associative cache controller 100 of a general type. During program execution, physical memory addresses 102 enter this cache controller 100 through processor port 104 from a translation lookaside buffer (not shown) associated with the processor. The physical memory address 102 is divided into three fields: a word-in-line portion 106 , a high-order portion 108 , and a bank address portion 110 . The set address section 110 is used as the set address and is used to retrieve the tag memory 112. The tag memory 112 has a number of cache way tags 114 at each set address, each cache way tag 114 having a way address field 116 and Road sign field 118 . The way flag field 118 includes valid bits 120 .
[0037] Comparator 122 compares way address field 116 with high order portion 108 of the physical memory address. The comparator match result is ANDed 124 with the valid bit 120 and other flags to determine a cache hit 126 and determine which...
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