Semiconductor memory device

Abstract

A semiconductor memory device, including a drive circuit 22 controls voltages applied to a substrate 1, selection gates SG 0 and SG 1, a local bit line LB 2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to the selection gate SG 0, a voltage lower than the voltage applied to the selection gate SG 0 to the selection gate SG 1, and a positive voltage to the local bit line LB 2, the drive circuit 22 controls so that electrons are selectively drawn out of a floating gate FG 3 to the local bit line LB 2 by F-N tunneling during writing operation. Sufficient operation margin is obtained even when memory cells are miniaturized.

Description

technical field [0001] The present invention relates to a semiconductor storage device, in particular to a rewritable non-volatile semiconductor storage device. Background technique [0002] Among conventional nonvolatile semiconductor memory devices, a nonvolatile semiconductor memory device as shown in FIGS. 10 to 12 is known (see Patent Document 1; Conventional Example 1). The nonvolatile semiconductor memory device according to Conventional Example 1 has, in the memory cell array, a first diffusion region 107, a selection gate 103, a second diffusion region (121 in FIG. 10), a floating gate 106, and a control gate. 111 (refer to FIGS. 10 and 11 ). [0003] The first diffusion regions 107 extend along one direction and are separated and juxtaposed on the surface of the substrate 101 . The first diffusion region 107 is used as a local bit line (LB). The selection gate 103 (SG) is disposed on the substrate 101 in a region between adjacent first diffusion regions 107 via ...

AI Technical Summary

Problems solved by technology

[0014] However, if the variation in the characteristics of the memory cell increases with the miniaturization of the memory cell, the variation in the threshold voltage Vt at the time of collective erasing increases, and it may not be possible to ensure a sufficient operating margin (write state ( Refer to FIG. 17(A)) and the difference in the threshold voltage Vt of the erased state (see FIG. 17(C))

If the erasing level is reduced in order to ensure a sufficient operating margin, most of the arbitrary memory cells in the erasing block will be in a depletion (depression) state (threshold voltage Vt is below 0V (L'); refer to FIG. 17 (B)), the selective write-back operation cannot be performed, and the operation may not be possible

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