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Processor

A processor and arithmetic processing technology, applied in the field of processors, can solve problems such as drawbacks and increased delay, and achieve the effect of high operating frequency and reducing delay

Inactive Publication Date: 2007-09-26
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0027] However, in the prior art described above, there is a problem that when data is output from the memory 14 to the register file 30, it is necessary to pass through the data conversion circuit 20, so the delay generated between the memory 14 and the register file 30 increase, this delay becomes a disadvantage in the development of processors that operate at high operating frequencies

Method used

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Embodiment approach 1

[0124] Next, Embodiment 1 of the present invention will be described with reference to the drawings.

[0125] The processor according to Embodiment 1 is characterized in that data conversion such as configuration change, code extension, and zero extension is performed before data is output from the register file to the arithmetic unit, instead of being performed between the memory and the register file.

[0126] Based on the above points of view, the processor according to Embodiment 1 of the present invention will be described.

[0127] FIG. 3 is a diagram showing the configuration of a processor according to Embodiment 1. FIG.

[0128] As shown in the figure, the processor 100 includes a memory read control circuit 12 , a memory write control circuit 13 , a memory 14 , and an arithmetic unit 15 . Furthermore, an instruction decoding circuit 101 , a flag value generating circuit 102 , and a register file 110 are provided.

[0129] The instruction decoding circuit 110 output...

Embodiment approach 2

[0190] Next, Embodiment 2 of the present invention will be described with reference to the drawings.

[0191] The processor according to Embodiment 2 is characterized in that before outputting data from the register file to the arithmetic unit, data conversion such as configuration change, code extension, and zero extension is performed inside the register file instead of between the memory and the register file. .

[0192] Based on the above points of view, the processor according to Embodiment 2 will be described.

[0193] In addition, the same code|symbol is attached|subjected to the same component as Embodiment 1, and description is abbreviate|omitted.

[0194] FIG. 9 is a diagram showing the configuration of a processor according to Embodiment 2. FIG.

[0195] As shown in the figure, the processor 200 differs from the processor 100 according to Embodiment 1 in that it includes a register file 210 instead of the register file 110 (see FIG. 3 ).

[0196] Compared with th...

Embodiment approach 3

[0220] Next, Embodiment 3 of the present invention will be described with reference to the drawings.

[0221] The processor according to Embodiment 3 is characterized in that data conversion such as configuration change, code extension, and zero extension is performed inside the arithmetic unit and the memory write control circuit, instead of between the memory and the register file.

[0222] Based on the above points of view, the processor according to Embodiment 3 will be described.

[0223] In addition, the same code|symbol is attached|subjected to the same component as Embodiment 1, and description is abbreviate|omitted.

[0224] FIG. 13 is a diagram showing the configuration of a processor according to Embodiment 3. FIG.

[0225] As shown in the figure, the processor 300 differs from the processor 100 according to Embodiment 1 in the following points (1) to (3) (see FIG. 3 ).

[0226] (1) The register file 310 is provided instead of the register file 110 .

[0227] The...

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Abstract

There is provided a processor capable of performing operation with a high operation frequency by reducing the delay generated between a memory and a register file. The processor (100) includes a register file (110) having a plurality of registers and a tag value generation circuit (102) for generating a tag value indicating the data attribute. Each of the registers has a data filed (112) for holding data and a tag field (111) for holding a tag value. When executing a load instruction for loading data into the register of the register file (110) from the memory (14), the tag generation circuit (102) generates a tag value according to the load instruction and stores it in the tag field (111).

Description

technical field [0001] The present invention relates to a processor capable of operating at a high operating frequency, and more particularly to a processor capable of increasing the operating frequency. Background technique [0002] There is now a processor that, when executing a load instruction, stores the data output from the memory after performing data transformation such as configuration change, code extension, zero extension, etc., according to the attributes of the data determined by the load instruction. in the register file (for example, refer to Patent Document 1). [0003] FIG. 1 is a diagram showing the configuration of a conventional processor. [0004] As shown in the figure, the processor 10 includes an instruction decoding circuit 11 , a memory read control circuit 12 , a memory write control circuit 13 , a memory 14 , an arithmetic unit 15 , a data conversion circuit 20 and a register file 30 . In addition, the register file 30 includes a plurality of re...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/34
CPCG06F9/30043G06F9/30192G06F9/30105
Inventor 深井慎一郎
Owner PANASONIC CORP
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