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Image data processing apparatus and method

A technology for image data and processing devices, which is applied in the field of encoding and decoding of video data, can solve problems such as difficult high-speed access to memory, and achieve the effect of reducing capacity and reducing capacity

Inactive Publication Date: 2007-10-31
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] That is, as shown in FIG. 49, in the data processing system 1 using an arithmetic processing device, the cache memory 2 is composed of a memory that can be accessed at high speed such as SRAM, and the main memory 4 is composed of a memory having a lower performance than the cache memory 2. Consumable memory structure, but this memory is difficult to access at high speed compared with the cache memory 2

Method used

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  • Image data processing apparatus and method
  • Image data processing apparatus and method
  • Image data processing apparatus and method

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Embodiment 2

[0142] FIG. 14 is a diagram showing the configuration of a buffer memory in a video device according to Embodiment 2 of the present invention with reference to FIG. 4 . In this embodiment, a shared flag is set for the data of each macroblock stored in the cache memory 32, and a reference macroblock overlapping among a plurality of macroblocks to be processed is identified by using the shared flag. Furthermore, the reference macroblock for which the shared flag has been set adjusts conflicting accesses from the macroblock processing engines 11A to 11C and 41A to 41C.

[0143] The setting of the flags can be performed for the macroblock processing engines 11A to 11C and 41A to 41C, and can be performed with a scheduler for separately managing the flags. The encoder and decoder of this embodiment have the same configuration as Embodiment 1 except for the configuration regarding flags.

[0144] The same effect as Embodiment 1 can be obtained by setting a flag and controlling acce...

Embodiment 3

[0146] 15 and 16A to 16C are diagrams for explaining macroblock processing in the video apparatus of Embodiment 3 of the present invention with reference to FIGS. 1 and 11A to 11C. In this embodiment, the post-processing section 13 described in Embodiment 1 is configured using a plurality of macroblock processing engines 43A, 43B, and 43C for post-processing. The encoder and decoder of this embodiment have the same configurations as those of Embodiment 1 except for the post-processing section 13 configured with a plurality of macroblock processing engines 43A, 43B, and 43C for post-processing. configuration.

[0147] Here, as in the case of the macroblock processing engines 11A to 11N and 41A to 41N in Embodiment 1, slices are sequentially and cyclically assigned to the respective macroblock processing engines 43A, 43B, and 43C for post-processing, and respectively assigned The multiple strips are processed sequentially in raster scan order. In addition, the engines perform ...

Embodiment 4

[0152] 17 and 18A to 18C are diagrams for explaining macroblock processing in a video apparatus according to Embodiment 4 of the present invention with reference to FIGS. 1 and 11A to 11C. In this embodiment, image data is encoded and decoded by MPEG-4. The encoder and decoder of this embodiment have the same configurations as those of Embodiment 1 except for the format-related configuration.

[0153] Here, in the intra prediction of MPEG-4, as described with reference to FIG. 44 , the adjacent macroblock (X-1, Y) on the scan start side in the same slice, The immediately above adjacent macroblock (X, Y-1) and the adjacent macroblock (X-1, Y -1) is set as the reference macroblock of the macroblock (X, Y).

[0154] Therefore, in this embodiment, as in the case of the macroblock processing engines 11A to 11N and 41A to 41N in Embodiment 1, slices are sequentially and circularly assigned to the respective macroblock processing engines, and a plurality of slices respectively assi...

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Abstract

An image data processing apparatus includes: plural arithmetic processing sections; a main memory; and a cache memory, wherein slices of the image data are sequentially and cyclically assigned to the plural arithmetic processing sections and plural slices to be processed are set as objects of processing, respectively, and the plural arithmetic processing sections process the image data in parallel to establish a consistent relationship of the processing of each slice with processing of the immediately preceding slice, in which the current slice and the immediately preceding slice can be simultaneously processed in parallel so that a reference macroblock of the macroblock in processing in the current slice may partly overlap with a reference macroblock of the macroblock in processing in the immediately preceding slice.

Description

technical field [0001] The present invention is applicable, for example, to the encoding and decoding of video data according to the H.264 / MPEG-4 AVC (ITU-T Rec. II. 264 ISO / IEC 14496-10 AVC) standard. The present invention reduces the capacity of the buffer memory in a configuration in which image data is simultaneously processed using a plurality of arithmetic processing devices for encoding processing and decoding processing in parallel by sequentially and circularly allocating slices to a plurality of an arithmetic processing section that simultaneously encodes and decodes image data in parallel using a plurality of arithmetic processing sections, and sets processing for each slice to establish a relationship in which processing is performed in each slice A reference macroblock of a macroblock may partially overlap a reference macroblock of a macroblock in the immediately preceding slice. Background technique [0002] In the prior art, in various video devices, H.264 / MP...

Claims

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Application Information

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IPC IPC(8): H04N7/26H04N7/30H04N7/32H04N7/50H04N19/00H04N19/426H04N19/436H04N19/51H04N19/60H04N19/625H04N19/91
CPCH04N19/00781H04N19/00509H04N19/00521H04N7/26744H04N19/00515H04N19/00484H04N19/61H04N19/423H04N19/43H04N19/433H04N19/436H04N19/42
Inventor 伊东义之福岛哲哉柳田幸雄
Owner SONY CORP
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