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Method for manufacturing layer structure

一种层结构、中间层的技术,应用在半导体/固态器件制造、电气元件、电路等方向,能够解决费用等问题

Inactive Publication Date: 2007-11-07
SILTRONIC AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of these methods is the expense they require

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0014] A 4μm thick SiGe layer is epitaxially deposited on a 300mm silicon substrate, where the germanium concentration is increased by 0 to 20% in the layer thickness. At 40×40μm 2 The roughness of the layer showed an RMS value of 100  when AFM was performed on the area of ​​?? The epitaxially coated substrate is then smoothed by processing with the method described. To this end, spray with water at 40°C in the etching chamber, and then use HF gas and ozone to perform etching. After being treated twice in this cycle, the substrate was sprayed with water again and centrifuged to dry. In this case, a total of 0.2 μm was removed from the SiGe layer. With 40×40μm 2 The AFM measurement performed in the area indicated that the RMS roughness was improved to 3 Ȧ.

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PUM

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Abstract

Laminar structure production produces a structure with a smoothed intermediate layer and another layer lying on top of it. The intermediate layer is treated with a gaseous etching agent containing hydrogen fluoride. Some material is thereby eroded, causing the intermediate layer to be made smooth.

Description

Technical field [0001] The present invention relates to a method of manufacturing a layer structure including a smoothed intermediate layer and a cover layer applied on the intermediate layer. Such layer structures are manufactured, for example, as substrates for electronic, optoelectronic and micro-electromechanical applications. For example, the layer is deposited on the carrier by the CVD method, or the layer is connected with the substrate by the bonding method. Representatives of these substrates are, for example, semiconductor wafers that include more deposited layers or connecting layers, especially SOI substrates (silicon on insulator), including Si x Ge 1-x (Silicon-germanium) layer and substrate of strained silicon (strained silicon on bulk) and sSOI substrate (strained silicon on insulator). Background technique [0002] Applying the cover layer to the intermediate layer is a critical step, because usually this step must require the lowest possible micro-roughness of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/20H01L21/762H01L21/84H01L21/306H01L21/311C23F1/12
CPCH01L21/02049C23F1/12
Inventor 迭戈·费若京特·施瓦布托马斯·布施哈尔特
Owner SILTRONIC AG
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