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Multiple banks read and data compression for back end test

A technology of test data and storage library, applied in the direction of information storage, static memory, digital memory information, etc.

Inactive Publication Date: 2007-11-14
QIMONDA +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While such compression reduces the amount of test data that must be processed, having to access a single repository at a time limits the throughput of front-end tests

Method used

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  • Multiple banks read and data compression for back end test
  • Multiple banks read and data compression for back end test
  • Multiple banks read and data compression for back end test

Examples

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Embodiment Construction

[0018] Detailed Description of Preferred Embodiments

[0019] Embodiments of the present invention generally provide methods and apparatus that can be used to increase backend testing throughput by allowing simultaneous access to multiple repositories. Especially when it is only necessary to indicate whether a device passed or failed and not necessarily the specific location of the failure, the techniques described here take advantage of the compression that can be achieved in back-end testing.

[0020] Descriptions of embodiments of the invention herein will refer to embodiments of a DRAM device utilizing two banks of memory cells accessed in parallel, where each bank has four banks. However, those skilled in the art will appreciate that the concepts described herein are generally applicable to accessing widely different arrangements having different numbers of bank groups and additionally different numbers of banks in each group.

[0021] The description of embodiments of t...

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Abstract

Methods and apparatus that may be used to increase back-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the compression that may be achieved in back-end testing, particularly when only an indication of whether a device has passed or failed is required and no indication of a particular location of a failure is necessary.

Description

[0001] Cross References to Related Applications [0002] This application relates to Serial No._ / _._, Attorney Docket No. INFN / 0242, entitled "PARALLEL READ FOR FRONT END COMPRESSIONMODE" filed on the same date as this application U.S. Patent Application for , which is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates generally to semiconductor testing and, more particularly, to testing dynamic random access memory (DRAM) devices. Background technique [0004] The development of sub-micron CMOS technology has led to an increase in demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo-static random access memory (PSRAM) devices, and the like. Here, these memory devices are collectively referred to as DRAM devices. [0005] During the manufacturing process, multiple DRAM devices are typically fabricated on a single silicon wafer and undergo some form of testing (c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4078G11C29/40
CPCG11C29/40G11C2029/2602G11C29/26
Inventor K·费基哈-罗姆达恩P·特鲁昂
Owner QIMONDA