Semiconductor memory device testing on/off state of on-die-termination circuit during data read mode, and test method of the state of on-die-termination circuit

Abstract

A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT state information signal indicating whether the ODT circuit is on or off, in response to an ODT control signal during a data read mode when data is output from memory cells. With a semiconductor memory device and method capable of testing whether an ODT resistor is on or off during a data read mode, it is possible to test whether an ODT circuit is on or off during reading of data.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2006-0025678 filed with the Korean Intellectual Property Office on Mar. 21, 2006, the contents of which are hereby incorporated by reference in their entirety. technical field [0003] The present invention relates to a semiconductor memory device having an on-die termination (ODT) circuit, and more particularly, to a semiconductor memory capable of testing the on / off state of the on-die termination (ODT) circuit in a data read mode parts and methods. Background technique [0004] In systems where signals are exchanged, a termination resistor (termination resistor) that terminates the bus is typically used to provide impedance matching. The terminating resistor improves received signal integrity by suppressing signal reflections. [0005] Termination resistors may be located outside or inside the semiconductor memory device. Termination resistors...

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Problems solved by technology

[0009] However, the conventional semiconductor memory device 100 can only recognize the resistance values ​​of the first ODT resistor R1 and the second ODT resistor R2 when no data read operation is performed.

Accordingly, the conventional semiconductor memory device 100 cannot judge whether the ODT circuit 130 is turned on or off during the data read operation.

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