Plasma display panel drive method and plasma display device
A technology for display panels and driving methods, applied to static indicators, instruments, etc., which can solve problems such as voltage rise, unstable write discharge, and image display quality deterioration
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no. 1 approach
[0047]Fig. 1 is an exploded perspective view showing important parts of a panel used in a first embodiment of the present invention. The panel 10 has a structure in which a glass front substrate 21 and a rear substrate 31 are arranged facing each other, and a discharge space is formed therebetween. A plurality of pairs of scan electrodes 22 and sustain electrodes 23 forming display electrode pairs are formed on the front substrate 21 parallel to each other. Furthermore, a dielectric layer 24 is formed so as to cover the scan electrodes 22 and the sustain electrodes 23 , and a protective layer 25 is formed on the dielectric layer 24 . In addition, a plurality of data electrodes 32 covered by an insulator layer 33 are disposed on the back substrate 31 , and a well-shaped barrier rib 34 is disposed on the insulator layer 33 . In addition, the fluorescent layer 35 is provided on the surface of the insulator layer 33 and the side surfaces of the barrier ribs 34 . Front substrate ...
no. 2 approach
[0096] The panel structure in this embodiment is the same as that in the first embodiment, and thus description thereof will be omitted. Also, the circuit blocks of the plasma display device are the same as those in FIG. 3 , but the lighting ratio calculation circuit 58 compares the lighting ratios between subfields having the same luminance weight in the current field and the previous field. Then, timing generation circuit 55 controls the timing signal supplied to sustain electrode drive circuit 54 based on the comparison result in lighting rate calculation circuit 58 and the detected lighting rate.
[0097] FIG. 10 is a diagram showing the relationship among subfields, lighting ratios, and erasing phase difference Th1 in the second embodiment of the present invention. In the first SF to the fourth SF, the erasing phase difference Th1 is controlled to be 150 ns regardless of the lighting rate. On the other hand, in the 5th SF to the 10th SF, the phase difference Th1 is switc...
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