HDLC data uplink and downlink method and communication device in RRU network

Abstract

The invention discloses a HDLC data downstream and upstream method and a communication device in a RRU network. The data downstream method includes: FPGA receives data frames, and detects whether the data frames are corresponding level data or next level data, according to the data frames address information, after determining the data frames contain valid data; if the data frames are the corresponding level data, perform decoding and CRC examination, store in a cache unit and notify CPU to read out the corresponding level data in the cache unit; if the data frames are the next level data, send to next level RRU. The invention also provides the data upstream method and the data downstream and upstream communication device. The invention adopts FPGA, implements separated processing to the downstream or the upstream corresponding level data and non corresponding level data, reduces CPU work load and can adopt low speed CPU with cost reduction. If the CPU on the corresponding level breaks down, the transmission of the next level data will not be influenced. The invention improves data transmission stability.

Description

【Technical field】 [0001] The invention relates to the technical field of communication, in particular to a method for downlinking and uplinking of high-level data link control (HDLC) data in a remote radio frequency unit (RRU) network and a communication device. 【Background technique】 [0002] High-level Data Link Control (HDLC) is a transmission protocol in the field of communication. In the remote radio unit (RRU) network system, HDLC data transmission is no longer a simple point-to-point mode, and HDLC frames need to be multiplexed and demultiplexed according to the network topology and RRU address information. As shown in Figure 1, in a current RRU network system using chain networking mode, the multiplexing and demultiplexing methods for HDLC frames are: [0003] For the downlink HDLC link, RRU0 first receives the downlink HDLC data from optical port 0 and decodes it, then extracts the HDLC data from the decoded data according to the RRU address of the current level an...

AI Technical Summary

Problems solved by technology

[0005] In the above-mentioned system, because the HDLC chip itself cannot recognize the address, the CPU is generally used for demultiplexing and multiplexing, which takes up more CPU resources. In the RRU system, the HDLC link rate is 480-1920 kbit / s , the general CPU cannot complete such high-speed processing, generally need to use high-speed CPU, the cost is very high

[0006] Secondly, since the data of the current level and non-level data are all processed by the CPU, as long as the CPU of the first level fails, the transmission will be interrupted

[0007] Again, the capacity of the data memory in the chip is limited, usually only a few bytes of first-in-first-out memory (FlFO) are available. When the capacity of the data cache needs to be expanded, the ASlC chip can only be connected with an external memory or other circuits, which not only increases the cost, but also increases the cost. and increase the complexity of the system

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