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Semiconductor element and wafer level chip size package having it

A wafer-level chip and size packaging technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device parts, electrical components, etc., can solve the problem of not fully avoiding the overall bending of CSP501, so as to avoid bending, increase the total area, and improve freedom. degree of effect

Inactive Publication Date: 2008-06-11
YAMAHA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it is difficult to avoid occurrence of overall bending of the CSP 501 including the semiconductor chip 503
[0048] That is, forming the V-shaped channel portion 506 on the surface and backside of the bottom substrate 502 cannot sufficiently prevent the overall bending of the CSP 501 including the semiconductor chip 503
[0049] Similar to CSP 501, it is difficult to avoid occurrence of overall bowing of WLCSP 511 including silicon substrate 512

Method used

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  • Semiconductor element and wafer level chip size package having it
  • Semiconductor element and wafer level chip size package having it
  • Semiconductor element and wafer level chip size package having it

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Embodiment Construction

[0164] The present invention will now be further specifically described by way of examples with reference to the accompanying drawings.

[0165] 1. The first embodiment

[0166] will now refer to figure 1 , 2 , 3, 4A-4F and 5 to describe the semiconductor device according to the first embodiment of the present invention. Such as figure 1 and 2 As shown, the semiconductor device 1 includes: a semiconductor chip 3 having a rectangular plate-like shape in a plan view; an insulating layer 5 (used as a first insulating layer) formed on a surface 3a of the semiconductor chip 3; A plurality of connecting electrodes 7 and radiating electrodes 9 provided on it; a plurality of wiring portions 11, 13 and 15 formed on the surface 5a of the insulating layer 5 to establish mutual connection between the semiconductor chip 3 and the connecting electrodes 7 or radiating electrodes 9 and a molding resin 17 (used as a second insulating layer) that covers the surface 5a of the insulating l...

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PUM

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Abstract

The invention relates to a semiconductor device encapsulated in a wafer level chip size package, including a metal post surrounded in the resin and formed on the re-wiring layer connected with a pad electrode; and an outer terminal connected with the surface of the metal post, wherein, the shape of the metal post is amended so that the first surface positioned near to the outer electrode is larger than the second surface positioned near to the re-wiring layer.

Description

[0001] This application is a divisional application of the No. 200510074168.8 invention patent application filed on March 11, 2005, entitled "Semiconductor Element and Wafer Level Chip Scale Package thereof". technical field [0002] The present invention relates to a semiconductor component and its Wafer Level Chip Scale Package (WLCSP). Background technique [0003] In semiconductor devices such as LSI devices, integrated circuits such as transistors and various electronic components are formed on the surface of a semiconductor chip and thus generate heat when they are operated. In order to avoid errors and malfunctions due to excessive heat generated in semiconductor chips, various heat sink structures and heat dissipation structures for effectively dissipating heat from semiconductor devices have been developed. For example, Japanese Patent Application Laid-Open No. 2002-158310 teaches a semiconductor device equipped with a heat dissipation structure in which heat dissip...

Claims

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Application Information

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IPC IPC(8): H01L23/485H01L23/34
CPCH01L2924/01019H01L2924/01322H01L2924/10158H01L2924/01066H01L2924/01078H01L2924/01067H01L2924/01068H01L2924/3025H01L2924/09701H01L2224/16H01L2224/13
Inventor 野本健太郎井川郁哉齐藤博佐藤隆志大桥敏雄大仓喜洋
Owner YAMAHA CORP