Buffer in ultra-low power consumption integrated circuit

Abstract

The invention discloses a buffer in an integrated circuit with ultra low power consumption. The invention applies voltage generated by two first level inverters to drive a second level inverter to reach a target of the buffer; at the same time, the wide length ratios of a PMOS pipe and a NMOS pipe in the two first level inverters are different from each other, thus leading to a different on-stage time, so that time points of the generated voltage reaching the second level inverter are different, which can prevent the PMOS pipe and the NMOS pipe in the second level inverter from being on at the same time and thus generate on-state current. The invention can be used in the integrated circuit with ultra low power consumption.

Description

technical field [0001] The present invention relates to buffers, and more particularly to buffers used in low power integrated circuits. Background technique [0002] In integrated circuit design, buffer design is generally realized directly by using several inverters in series, such as figure 1 A circuit of a traditional buffer is shown, which includes two-stage inverters, the first-stage inverter includes an enhancement-mode PMOS transistor M1 and an enhancement-mode NMOS transistor M3 connected in series, and the second-stage inverter includes a series-connected The enhanced PMOS transistor M2 and the enhanced NMOS transistor M4, the output of the first stage inverter is used as the input of the second stage inverter, the signal still maintains the original level after two stages of inversion, but the time delay, thus achieve the function of the buffer. [0003] This circuit structure is simple, but when the output voltage of the first-stage inverter jumps from "high" t...

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Problems solved by technology

[0003] This kind of circuit structure is simple, but when the output voltage of the first-stage inverter jumps from "high" to "low" or from "low" to "high", it will make the PMOS transistor M2 and the NMOS transistor M4 be at the same time. In the sub-threshold state, the two tubes are turned on at the same time, and a large pass-through current is generated at this time, which should be avoided as much as possible for low-power integrated circuit design

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