Buffer in ultra-low power consumption integrated circuit

Abstract

The invention discloses a buffer in an integrated circuit with ultra low power consumption. The invention applies voltage generated by two first level inverters to drive a second level inverter to reach a target of the buffer; at the same time, the wide length ratios of a PMOS pipe and a NMOS pipe in the two first level inverters are different from each other, thus leading to a different on-stagetime, so that time points of the generated voltage reaching the second level inverter are different, which can prevent the PMOS pipe and the NMOS pipe in the second level inverter from being on at the same time and thus generate on-state current. The invention can be used in the integrated circuit with ultra low power consumption.

Description

Technical field

[0001] The present invention relates to buffers, and in particular to buffers used in low power consumption integrated circuits. Background technique

[0002] In the design of integrated circuits, the buffer design is generally realized by directly using several inverters in series. As shown in Figure 1, a traditional buffer circuit includes two stages of inverters. The phaser includes an enhanced PMOS tube M1 and an enhanced NMOS tube M3 connected in series. The second stage inverter includes an enhanced PMOS tube M2 and an enhanced NMOS tube M4 connected in series. The output of the first stage inverter is used as the second The input of the stage inverter, the signal still maintains the original level after two stages of inversion, but the time delay, so as to achieve the buffer function.

[0003] This circuit structure is simple, but when the output voltage of the first stage inverter changes from "high" to "low" or from "low" to "high", the PMOS tube M2 and th...

Images