Buffer in ultra-low power consumption integrated circuit

An integrated circuit, ultra-low power consumption technology, applied in the buffer field, can solve the problem of large punch-through current, and achieve the effect of avoiding conduction current

Active Publication Date: 2010-08-18
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] This kind of circuit structure is simple, but when the output voltage of the first-stage inverter jumps from "high" to "low" or from "low" to "high", it will make the PMOS transistor M2 and the NMOS transistor M4 be at the same time. In the sub-threshold state, the two tubes are turned on at the same time, and a large pass-through current is generated at this time, which should be avoided as much as possible for low-power integrated circuit design

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Embodiment Construction

[0018] The present invention will be further described below with reference to FIG. 2. In FIG. 2, two first-stage inverters A1 and A2 are included. Among them, the first-stage inverter A1 includes a PMOS tube M1 and an NMOS tube M2 connected in series, and a PMOS tube The gate of M1 is connected to the gate of the NMOS tube M2 and connected to the voltage input terminal Vi. The gate of the PMOS tube M1 and the gate of the NMOS tube M2 are connected and converged at point C and used as the first-stage inverter A1 At the output end, the source of the PMOS tube M1 is connected to the power supply voltage, and the source of the NMOS tube M2 is grounded. The first-stage inverter A2 includes a PMOS tube M3 and an NMOS tube M4 connected in series. The gate of the PMOS tube M3 is connected to the gate of the NMOS tube M4 and connected to the voltage input terminal Vi. The gate of the PMOS tube M3 is connected to the NMOS tube. The gate of M4 converges at point D and serves as the outpu...

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Abstract

The invention discloses a buffer in an integrated circuit with ultra low power consumption. The invention applies voltage generated by two first level inverters to drive a second level inverter to reach a target of the buffer; at the same time, the wide length ratios of a PMOS pipe and a NMOS pipe in the two first level inverters are different from each other, thus leading to a different on-stagetime, so that time points of the generated voltage reaching the second level inverter are different, which can prevent the PMOS pipe and the NMOS pipe in the second level inverter from being on at the same time and thus generate on-state current. The invention can be used in the integrated circuit with ultra low power consumption.

Description

Technical field [0001] The present invention relates to buffers, and in particular to buffers used in low power consumption integrated circuits. Background technique [0002] In the design of integrated circuits, the buffer design is generally realized by directly using several inverters in series. As shown in Figure 1, a traditional buffer circuit includes two stages of inverters. The phaser includes an enhanced PMOS tube M1 and an enhanced NMOS tube M3 connected in series. The second stage inverter includes an enhanced PMOS tube M2 and an enhanced NMOS tube M4 connected in series. The output of the first stage inverter is used as the second The input of the stage inverter, the signal still maintains the original level after two stages of inversion, but the time delay, so as to achieve the buffer function. [0003] This circuit structure is simple, but when the output voltage of the first stage inverter changes from "high" to "low" or from "low" to "high", the PMOS tube M2 and th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0185H03K19/0175H03K19/003
Inventor 王坤李向宏刘新东
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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