34results about How to "Small conduction current" patented technology

The invention provides a separation method and a corresponding transferring method comprising separating a detached member from a substrate, wherein the separation of the detached member from the substrate consists of continuous beam irradiation; a first beam irradiation irradiating a first area, a second beam irradiation irradiating a second area, the two areas overlapped with each other. The invention also provides a manufacture method for thin film device with application of the separation method and the transferring method.

A transfer method comprising: providing a substrate; forming a transferred layer on the substrate; combining a transfer body with the transferred layer; and removing the transferred layer from the substrate, and transferring the transferred layer to the Transfer body; re-use the above substrate for another transfer.

The invention relates to a gate structure of a semiconductor device. The gate structure comprises a gate oxide layer, a field oxide structure and a poly-silicon split gate, wherein the gate oxide layer is arranged on a substrate, the field oxide structure is arranged on the gate oxide layer, the poly-silicon split gate is arranged on the gate oxide layer and the field oxide structure, the width of the field oxide structure is smaller than the distance of two surfaces, deviating from each other, between a first gate structure and a second gate structure, and greater than the distance between the first gate structure and the second gate structure, and the orthographic projection of an interval region between the first gate structure and the second gate structure on the field oxide structure is not beyond the edge of the field oxide structure. The invention also relates to a fabrication method for the gate structure of the semiconductor device. The fabrication method is compatible and consistent with the traditional fabrication methods of a power vertical double-diffusion metal oxide semiconductor field effect transistor (VDMOS) and an insulated gate bipolar transistor (IGBT) chip, the process difficulty and the photoetching frequency are not increased, the specific turn-on resistance, the gate charge Qg and the leakage current Idss are low, the reliability is high, the chip area is small, the production cost can be greatly reduced, and the fabrication method can be used for manufacturing the power VDMOS and the IGBT chip at a large scale, low cost and high reliability.

The invention discloses a low-temperature drift delay circuit. The circuit includes: a bias current source circuit, a slope voltage generating circuit and a fixed threshold switch circuit; the bias current source circuit is used to generate a negative temperature coefficient current bias, Its input terminal is connected to the power supply voltage, and its output terminal is connected to the slope voltage generating circuit; the bias input terminal of the slope voltage generating circuit is connected to the output terminal of the bias current source circuit, and its digital signal input terminal is connected to the digital signal input , the output terminal of which is connected to the fixed threshold switch circuit; the input terminal of the pull-down switch of the fixed threshold switch circuit is connected to the output terminal of the slope voltage generating circuit, the input terminal of the pull-up switch is connected to the digital signal input, and the output terminal of the fixed threshold switch circuit is delayed subsequent digital signals. The invention can perform time-delay processing on digital signals without being affected by temperature and power supply voltage; the fixed threshold switch circuit adopts a thyristor structure as a pull-down switch, and has the advantages of stable threshold value, high speed, simple structure and the like.

The invention discloses an injection-locked frequency divider with dual-mode low power consumption and wide locking range, comprising a negative resistance unit, an injection unit, a resonant unit and a switched capacitor array unit, the negative resistance unit, an injection unit, a resonant unit and a switch The capacitor array units are connected in parallel with each other. In the present invention, by setting the negative resistance unit adopting the current multiplexing structure and substrate bias technology, the power supply voltage is reduced and the conduction current is reduced by half, and the performance of low power consumption is realized; by designing the switched capacitor array unit, the The switching signal controls the capacitance value of the capacitor array to achieve a wide range, which avoids the compromise design of power consumption and quality factor due to the locked range in circuit parameters, and does not increase power consumption significantly. The dual-mode frequency division is realized by setting the injection unit of the double-tube direct injection method, and the influence of the injection power on the wide range is reduced through the specific bias design of the injection tube, and the wide lock-in is maintained at a low injection power. range advantage.

The invention relates to a VDMOS, comprising: a semiconductor substrate, a body region formed in the substrate, and a source region formed in the body region; a trench runs through the source region and the body region and extends to the substrate, and each trench gate structure includes The gate dielectric layer on the inner wall of the trench and the gate layer filled in the trench; the first interlayer dielectric layer, the first metal layer, and the second interlayer dielectric layer are sequentially stacked on the source region and each trench gate structure. A dielectric layer and a second metal layer; one of the first metal layer and the second metal layer is a gate metal layer and is connected to each gate layer through a gate contact hole, and the other layer is used as a source metal layer and is connected to each gate layer through a gate contact hole. The source region contact hole is connected to the body region, and the number of trench gate structures located on the same side of the source region contact hole in each cell structure is N≥2. The number of trench gate structures on the same side as the contact hole in the source region of the cellular structure is N≥2, which can obtain a larger conduction current while occupying a small area of ​​the trench gate.

The invention discloses a buffer in an integrated circuit with ultra low power consumption. The invention applies voltage generated by two first level inverters to drive a second level inverter to reach a target of the buffer; at the same time, the wide length ratios of a PMOS pipe and a NMOS pipe in the two first level inverters are different from each other, thus leading to a different on-stagetime, so that time points of the generated voltage reaching the second level inverter are different, which can prevent the PMOS pipe and the NMOS pipe in the second level inverter from being on at the same time and thus generate on-state current. The invention can be used in the integrated circuit with ultra low power consumption.

The invention discloses a reading method and a flash memory device. The reading method is applied to the flash memory device comprising a nonvolatile semiconductor memory unit array. The method comprises the steps of judging whether to read all memory units of the nonvolatile semiconductor memory unit array, if yes, applying voltage to corresponding word lines of all memory units to perform a first sensing operation; and after the first sensing operation, performing a second sensing operation on the memory unit determined to be in a closed state, wherein a difference between the voltage applied to the word lines during the first sensing operation and the voltage applied to the work lines during the second sensing operation is within a preset range, and sensing time corresponding to the second sensing operation is not less than that corresponding to the first sensing operation. According to the technical scheme of the method and the device provided by the invention, the flash memory device can be read via the two sensing operations, and thus noise of a common source line is reduced, and accuracy of the reading operation is ensured.

The invention discloses a multi-mode output driven type presser foot lifting electromagnet control system. The system comprises a driving circuit, a control circuit and a work circuit, wherein the driving circuit comprises a power unit, a first diode and a capacitor unit; the control circuit comprises a micro processor and a resistor unit; the work circuit comprises a switch unit, an electromagnetand a second diode; the micro processor controls the power unit to output linear adjustable direct-current voltage, and the voltage can be adjusted to 0 V; the micro processor controls the switch unit to be switched on or off. By means of the multi-mode output driven type presser foot lifting electromagnet control system, the problem is solved that when continuously working, the electromagnet istoo hot and damaged, and the problems are solved that in the process that the lifting state of a presser foot is changed into a lowering state of the presser foot, the mechanical shock between the presser foot and the contact surface is large, so that the device is short in service life and a fabric is damaged, and it is achieved that the electromagnet is quickly started.

The invention discloses a power-on reset circuit of an electronic label of an RFID (radio frequency identification device) system, which comprises two input ends, one output end, nine MOS (metal oxide semiconductor) transistors, one resistor and two capacitors, wherein input signals (voltage drain drain (VDD)) of the first input end and the second input end are working voltage signals output by a regulator of a radio-frequency analog front end circuit of the electronic label of the RFID system; and output signals (power-on reset (POR)) of the output end are power-on reset signals provided by a digital baseband circuit of the electronic label of the RFID system. The power-on reset circuit has an extremely low breakover current, and achieves the purpose of low power consumption.