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Semiconductor structure and forming method thereof, and SRAM device

A technology of semiconductor and gate structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc. The probability of channel leakage current, the effect of improving electrical performance and strong control ability

Pending Publication Date: 2022-05-27
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur

Method used

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  • Semiconductor structure and forming method thereof, and SRAM device
  • Semiconductor structure and forming method thereof, and SRAM device
  • Semiconductor structure and forming method thereof, and SRAM device

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Embodiment Construction

[0015] It can be known from the background art that the devices formed at present still have the problem of poor performance. Now combined with a method of forming a semiconductor structure, the reasons for the poor performance of the device are analyzed.

[0016] refer to Figure 1 to Figure 3 , showing a schematic structural diagram of key steps in a method for forming a semiconductor structure.

[0017] like figure 1 As shown, a substrate is provided, the substrate including a first device region I and a second device region II, the substrate including a substrate 1 and a channel stack 2 on the substrate 1, the channel stack 2 includes a sacrificial layer 21 and a channel layer 22 on the sacrificial layer 21 ; a dummy gate structure 4 spans the channel stack 2 , and the dummy gate structure 4 covers the channel stack 2 Part of the top wall and part of the sidewall are laterally parallel to the surface of the substrate 1 and perpendicular to the extension direction of the...

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Abstract

A semiconductor structure and a forming method thereof, and an SRAM device, the forming method comprising: providing a substrate, the substrate comprising a substrate, a plurality of channel stacks discrete on the substrate, and a dummy gate structure crossing the plurality of channel stacks, the dummy gate structure covering a portion of the top wall and a portion of the side wall of the channel stacks, the channel stacks comprising sacrificial layers and channel layers located on the sacrificial layers; forming a side wall covering the pseudo gate structure and exposing an interlayer dielectric layer at the top of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer; removing one or more channel layers at the top of the channel stack; removing the sacrificial layer to form a channel; a gate structure is formed in the gate opening and the channel. According to the embodiment of the invention, one or more channel layers at the top of the channel lamination layer are removed, so that the number of the channel layers in the semiconductor structure is reduced, the overall conduction current of the channels of the semiconductor structure is reduced when the semiconductor structure works, and the semiconductor structure can meet the process requirement.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure, a method for forming the same, and an SRAM device. Background technique [0002] In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, Metal-Oxide-Semiconductor Field-Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, The channel length of MOSFET) has also been shortened accordingly. However, with the shortening of the channel length of the device, the distance between the source electrode and the drain electrode of the device is also shortened, so the control ability of the gate structure to the channel becomes worse, and the gate voltage pinch off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage)...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L27/092H01L27/11H10B10/00
CPCH01L21/823807H01L21/823821H01L21/823828H01L27/0924H10B10/12
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP
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