Formation method of semiconductor structure

Abstract

The invention discloses a forming method of a semiconductor structure. The forming method comprises the following steps: providing a substrate, a pseudo gate structure, a source-drain doped region and an interlayer dielectric layer; removing the pseudo gate structure in the isolation region to form an isolation opening; performing first ion doping on the fin part below the isolation opening to form an isolation doped region, wherein the doping type of the isolation doped region is different from that of the source-drain doped region; filling an isolation structure in the isolation opening; removing the residual pseudo gate structure to form a gate opening; a gate structure is formed in the gate opening. According to the embodiment of the invention, the isolation doped region with the doping type different from that of the source-drain doped region is formed, so that the doping concentration of inversion ions in the fin part of the isolation region can be improved, the potential barrier of a PN junction formed by the source-drain doped region and the fin part of the isolation region is correspondingly improved, conduction current is prevented from being generated in the fin part of the isolation region when the device works, and the reliability of the device is improved. Therefore, the isolation between the fin parts in the isolation region and the fin parts in other regions is realized, and a fin cutting process is not needed, so that the fin parts are of a continuous structure, and stress release in the fin parts is avoided.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background technique [0002] In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to the smaller feature size, the Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET) channel length is correspondingly shortened. However, with the shortening of the channel length of the device, the distance between the source and the drain of the device is also shortened, so the control ability of the dummy gate structure to the channel becomes worse, and the gate voltage pinch off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects), more likely to occur. [0003] Th...

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Problems solved by technology

[0004] However, the performance of current FinFETs still needs to be improved

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