Semiconductor structure and manufacturing method thereof

Abstract

The application discloses an isolation structure of a semiconductor substrate, and the isolation structure is formed on the semiconductor substrate, comprising an isolation groove embedded in the semiconductor substrate and a dielectric layer filled in the isolation groove. The top of the isolation groove has a first width W1, and the bottom of the isolation groove has a second width W2, wherein W2 is greater than W1. The application also discloses a manufacturing method of the isolation structure, a semiconductor structure having the isolation structure and a manufacturing method thereof. The isolation structure and the manufacturing method thereof can improve the integration level of integrated circuits.

Description

technical field [0001] The present invention relates to the field of semiconductor structures and manufacturing thereof, in particular to an isolation structure of a semiconductor substrate and a manufacturing method thereof, as well as a semiconductor structure having the isolation structure and a manufacturing method thereof. Background technique [0002] Over the past few decades, the development of integrated circuits has almost strictly followed the famous Moore's Law proposed by Gordon Moore, one of the founders of Intel: the number of transistors that can be accommodated on an integrated circuit (IC) doubles approximately every 18 months , performance is also doubled. This is mainly achieved by the continuous scaling-down of IC size, especially the feature size of MOSFETs most commonly used in digital circuits, that is, the continuous reduction of channel length or gate pitch (pitch), and Technologies such as integration process, small-size packaging, and design for ...

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Problems solved by technology

However, since the width of the top opening of the shallow trench isolation 3 is large, in order to cover the shallow trench isolation 3 and protect its corner 7, the width of the dummy gate electrode 4 cannot be smaller than the width of the top opening of the shallow trench isolation 3, Therefore, while ensuring the isolation effect, it is difficult to further reduce the area occupied by the shallow trench isolation 3 and the dummy gate electrode 4 thereon, which in turn affects the proportional reduction of the entire MOSFET circuit area, making it difficult to continue to increase the integration level. and added process steps

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