The invention discloses an inclined silicon groove etching process. The process includes steps: forming a hard mask layer on the surface of a to-be-etched wafer, coating the surface of the hard mask layer with photoresist, and performing exposure and development to expose a to-be-etched hard mask layer window; performing hard mask etching at the exposed window, and etching to the surface of the wafer; performing silicon groove etching at the window subjected to hard mask etching, and etching to a set value of silicon groove depth, wherein etching gas is SF6, passivation gas comprises O2 and Hbr, bias power is 50-55W, bias power efficiency is 110-130Hz, bias power cycle is 65%-75%, and source radio-frequency power is 1000-1100W; removing photoresist in a non-silicon-groove area according toa dry-process photoresist removal method. A silicon groove side wall angle is optimized from 90 degrees to be close to 80 degrees; in a subsequent silicon groove filling process, voids formed after filling are eliminated, and accordingly breakdown voltage is increased, electric leakage is reduced, and reliability of a dielectric isolation integrated process is improved.