Frame synchronization detection method and device for OFDM system
A technology of orthogonal frequency division and detection method, which is applied in the field of wireless communication, can solve problems such as detection performance degradation, failure, and destruction of three-segment pseudo-periodic characteristics, and achieve the effect of solving synchronization problems and realizing OFDM frame synchronization
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Embodiment 1
[0045] Embodiment 1: Realize the frame synchronization detection based on the preamble conjugate symmetry characteristic by using FPGA.
[0046] Such as image 3 As shown, two receiving buffers Rx Buff1 and Rx Buff2 are set, both of length 2w+1 (w is the size of the conjugate correlation window, satisfying w≤(FFT_size) / 2).
[0047] The OFDM data signal is serially input into the receiving buffer Rx Buff1 after being converted by an analog-to-digital converter (AD Converter, ADC for short). When Rx Buff1 is full, take the data r(d) in the buffer as the axis of symmetry for mirror symmetry operation, and store the operated data in Rx Buff2. Usually, because the actual operation only uses half or less of the data in the buffer, the buffer Rx Buff2 in the present invention can also be replaced by the rest of the Rx Buff1. In the present invention, for convenience of description, two buffers are still used.
[0048] Use the data in the buffers Rx Buff1 and Rx Buff2 to perform fr...
Embodiment 2
[0054] Embodiment 2: Utilize DSP to realize frame synchronization detection based on the preamble conjugate symmetry characteristic.
[0055] The OFDM data signal is converted by the ADC and placed in the memory. At each calculation, the data of length 2w+1 is taken from the memory and placed in the register Rx Buff1, and then the Rx Buff1 is mirrored with the intermediate data as the axis of symmetry. The operated data is stored in Rx Buff2. The registers Rx Buff1 and Rx Buff2 are structured with image 3 The receive buffer structure shown is the same.
[0056] Then use the data in Rx Buff1 and Rx Buff2 to perform downlink frame detection calculation according to the formulas (1)-(4). The specific process is the same as that in Embodiment 1, so it will not be repeated.
[0057] It should be noted that the difference between the calculation method in Embodiment 2 and the method using FPGA calculation in Embodiment 1 is mainly that FPGA can perform parallel operations, so rea...
Embodiment 3
[0058] Embodiment 3: Using FPGA+DSP to realize frame synchronization detection based on the preamble conjugate symmetry characteristic.
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