Pulse density modulator used for TD-SCDMA and 4G terminal

A TD-SCDMA and pulse density modulation technology, which is applied in the field of pulse density modulators, can solve the problems of slow filter response speed and long modulation period, etc.

Inactive Publication Date: 2008-08-27
ZHEJIANG HUALI COMM TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, when the number of digits of the digital signal to be modulated increases, the modulatio

Method used

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  • Pulse density modulator used for TD-SCDMA and 4G terminal
  • Pulse density modulator used for TD-SCDMA and 4G terminal
  • Pulse density modulator used for TD-SCDMA and 4G terminal

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0079] Example 1: figure 1 It is a block diagram of the pulse density modulation system proposed in this design for TD-SCDMA, Beyond 3G, and 4G terminals. The pulse density modulation system consists of the following components:

[0080] (1) Controller with DSP as the core (No. 101)

[0081] (2) Pulse Density Modulator PDM (102)

[0082] (3) Clock generator (103)

[0083] (4) Pulse density modulator off-chip RC low-pass filter (104)

[0084] Wherein, the DSP 101 provides control signals for the pulse density modulator PDM 102 to control the level amplitude of the output signal of the pulse density modulator PDM 102 and the refresh rate of the output signal. The clock generator 103 provides a working clock signal for the pulse density modulator PDM 102 . An off-chip RC low pass filter 104 is then used to convert the output of the pulse density modulator PDM 102 into an analog signal.

[0085] In the above-mentioned pulse density modulation system, the pulse density modula...

Embodiment 2

[0103] Embodiment 2: The relationship between PDM 102 and the external and internal detailed input and output signals, such as image 3 shown.

[0104] The input and output signals of the DSP interface 201 are shown in Table 1.

[0105] The input and output signals of the clock gating unit 203 are shown in Table 2.

[0106] The input and output signals of the accumulator 204 are shown in Table 3.

[0107] The input and output signals of the clock divider 202 are shown in Table 4.

[0108] The input and output signals of the OR gate 205 are shown in Table 5.

[0109] The input and output signals of the output control circuit 207 are shown in Table 7.

[0110] The input and output signals of the reset circuit 208 are shown in Table 8.

Embodiment 3

[0111] Embodiment 3: PDM 102 outputs logic 1 and logic 0. Its output is passed through an analog low-pass off-chip filter to generate an analog value. When it outputs a high-level signal, the voltage is very close to the power supply voltage Vcc (3.3V in this design), and when it outputs a low-level signal, the voltage is very close to the ground GND voltage.

[0112] PDM 102 should have sufficient resolution to perform the above tasks. Currently, we expect 12-bit resolution. Also, the PDM 102 can output from V L to V H (where V L is the voltage corresponding to a logic low level, V H is the voltage corresponding to the logic high level) all voltage values ​​in the range. At the same time, the output of the PDM 102 can also be set to a high-impedance state Hi-Z (that is, the PDM output is set to output disable. Output disable is only performed on the output pin).

[0113] The refresh rate of PDM 102 can be set by DSP 101 using DSP software / firmware, with faster refresh ...

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Abstract

The invention proposes a pulse density modulator used for a TD-SCDMA terminal, a Beyond 3G terminal and a 4G terminal. The pulse density modulator (PDM) comprises a DSP interface, a clock gate control unit, a clock frequency divider, an accumulator, an OR gate, an output register, a reset circuit and an output control circuit. The output of the pulse density modulator is a simulation value generated by a simulation low-pass plate external filter. When the PDM outputs a high level signal, the voltage is very close to the source voltage Vcc; when the PDM outputs a low level signal, the voltage is very close to the ground voltage GND. The pulse density modulator (PDM) can have high resolution expressed by the multi-bit and output all voltage values in the range from the logic low level to the logic high level. The output of the pulse density modulator (PDM) can be set to be in a high resistance state; the refresh speed of the pulse density modulator (PDM) can be set by a DSP or a DSP software/firmware. When a plurality of pulse density modulators (PDM) are in use, all pulse density modulators (PDM) can be divided into groups; each group can include a plurality of pulse density modulators; each group of PDM can be enabled separately; the groups are controlled by the PDM clock enabling signal; each group of PDM is provided with a reset circuit; the PDM is reset and initialized to be in the high resistance state when the pulse density modulator (PDM) receives the reset signal of the DSP each time. When the pulse density modulator (PDM) is set to be the high rail level output or in the high resistance state, the internal clock frequency divider in the pulse density modulator (PDM) stops operating.

Description

technical field [0001] The invention provides a pulse density modulator for TD-SCDMA, B3G (Beyond 3G), 4G (fourth generation mobile communication) terminals, which belongs to the field of mobile communication technology manufacturing. Background technique [0002] In digital signal processing, it is often necessary to convert multi-bit digital signals into one-bit digital signals. For example, in the field of communication, the receiver needs to convert the encoded digital voice signal into an analog signal, that is, restore the original analog voice signal. Coded speech signal, usually a multi-bit bit stream. Therefore, how to convert multi-bit bit streams into analog voice signals has become the key to ensuring communication quality. As another example, in some control circuits, the control signal is a multi-bit digital signal generated by calculation, and these digital signals must be converted into analog signals to control the circuit. Therefore, how to convert multi...

Claims

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Application Information

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IPC IPC(8): H04B14/02H04B14/04H03K7/08
Inventor 许晓斌许雪琦
Owner ZHEJIANG HUALI COMM TECH
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