Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of disordered ferroelectric film crystals, degradation of FeRAM characteristics, etc., and achieve the effect of high exchange capacity
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no. 1 approach
[0043] An element isolation layer 111 is provided on the upper portion of the semiconductor substrate 110 for isolating each element region. In addition, a p-well 112 or an n-well (not shown) is provided in each element region separated by the element isolation layer 111 . like Figure 4 As shown, in the memory cell region, two transistors T1 and T2 are formed corresponding to one p-well 112 . That is, two gate electrodes 114 arranged in parallel to each other are formed on the p-well 112 of the memory region. Near the surface of p-well 112 on both sides of these gate electrodes 114, low-concentration n-type impurity regions 116 and high-concentration n-type impurity regions 118 serving as sources and drains of transistors T1 and T2 are formed.
[0044] A stopper layer 120 is formed on the semiconductor substrate 110 to cover the gate electrode 114 , and a first interlayer insulating film 121 is formed on the stopper layer 120 . Cu (copper) plugs 124 a and 124 b penetrating...
no. 2 approach
[0086] In this embodiment, if Figure 9 As shown in (b), plugs 224 a and 224 b corresponding to plugs 124 a and 124 b of the first embodiment are formed by laminating W film 221 and Cu film 222 . Therefore, the amount of Cu in the plugs 224a, 224b is reduced only by the amount corresponding to the W film 221, so even if, for example, the thickness of the adhesion layer 122 is reduced and the contamination prevention performance for Cu is reduced, the amount of Cu diffused into the interlayer insulating film 121 is reduced. Since the atomic weight of Cu is small, deterioration of the characteristics of the transistors T1 and T2 due to Cu contamination can also be suppressed.
[0087] Figure 10 (a) and (b) are sectional views showing the method of manufacturing the semiconductor device of the present embodiment. First, if Figure 10 As shown in (a), as in the first embodiment, an element isolation layer 111 , a p-well 112 , transistors T1 and T2 , a stopper layer 120 , and a...
no. 3 approach
[0097] In this embodiment, the plugs 234a, 234b corresponding to the plugs 124a, 124b of the first embodiment are formed of W (or polysilicon), and grooves (depressions or erosions) appear on the surface. Furthermore, a conductive adhesion layer 235 , a Cu film 236 , and a barrier metal 237 are formed between the plug 233 b and the ferroelectric capacitor 130 . The Cu film 236 is provided to compensate for grooves on the surface of the plug 234b, and the surface of the Cu film 236 on the ferroelectric capacitor side is flattened by low-pressure CMP polishing or ECMP polishing.
[0098] Figure 12 , Figure 13 It is a cross-sectional view showing the method of manufacturing the semiconductor device of the present embodiment. First, if Figure 12 As shown in (a), as in the first embodiment, an element isolation layer 111 , a p-well 112 , transistors T1 and T2 , a stopper layer 120 , and a first interlayer insulating film 121 are formed on a semiconductor substrate 110 . Afte...
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