Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer

Abstract

A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.

Description

technical field [0001] The present invention relates to a method of manufacturing a fin transistor, and in particular, to a method of manufacturing a fin transistor in which a spin-on-glass layer used as a material for a field insulating layer is prevented etching loss. Background technique [0002] As the design rules of semiconductor devices decrease, the channel length and width of transistors decrease accordingly. As a result, existing planar transistor structures are limited in realizing the threshold voltage required for highly integrated semiconductor devices with minimum line widths of less than 100 nm. In order to solve this problem, a fin transistor has been proposed in which an increase in driving current and required operating speed can be obtained by increasing a channel width. [0003] The fin transistor structure includes field insulators that are etched to create active areas with raised structures, and thus the line width of the transistor increases the he...

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Problems solved by technology

For example, in DRAM devices, the data retention time is shortened, making normal operation difficult and thus reducing the yield and reliability of the device

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