Semiconductor device and method of forming the same

Abstract

Semiconductor devices are disclosed that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate insulating layer and a gate electrode are stacked on a channel region between the first and second doped regions. Spacers are on opposite sidewalls of gate electrode. A first surface metal silicide layer extends across a top surface of the first doped region adjacent to the spacer. A second surface metal silicide layer extends across a top surface of the second doped region adjacent to the spacer. At least one insulation layer extends across the semiconductor substrate including the first and second surface metal silicide layers. A first contact plug extends through the insulation layer and contacts the first surface metal silicide layer. A second contact plug extends through the insulation layer, the second surface metal silicide layer, and the second doped region into the well within the semiconductor substrate. Related methods of forming semiconductor devices are disclosed.

Description

technical field [0001] The present invention relates to semiconductor devices and fabrication of semiconductor devices, and more particularly, to semiconductor devices having transistors and related fabrication techniques. Background technique [0002] A transistor may be formed on a semiconductor substrate to include source and drain regions defined in a well within the semiconductor substrate, and a gate electrode on a channel region between the source and drain regions. During operation, a well bias voltage is applied to the well to increase the operational stability of the transistor. As the level of integration increases, semiconductor device features continue to decrease and, therefore, the size of the well pick up region that can be used to apply well bias continues to decrease. [0003] FIG. 1 is a cross-sectional view of a conventional transistor with a structure that can be used to apply a well bias. Referring to FIG. 1, a well 2 is formed in a semiconductor subs...

AI Technical Summary

Problems solved by technology

As a result, the well voltages under transistors relatively far from the well pickup region 7 become insufficient to maintain stable operation of those transistors and may cause those transistors to lock up and / or degrade noise margins

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