Solid-state imaging device and camera

A solid-state imaging device and pixel technology, which is used in image communication, TV, color TV components, etc.

Inactive Publication Date: 2008-11-19
PANASONIC CORP
View PDF2 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Depending on the specification, pulses other than the electronic shutter pulse can also cause this periodic noise

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Solid-state imaging device and camera
  • Solid-state imaging device and camera
  • Solid-state imaging device and camera

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0059] FIG. 1 shows a general configuration of a solid-state imaging device related to a first embodiment of the present invention.

[0060] The solid-state imaging device 10 includes a pixel array 11 , a load circuit 12 , a row selection decoder 13 , a column selection decoder 14 , a signal processing unit 15 and an output amplifier 16 .

[0061] The pixel array 11 includes a plurality of pixels arranged two-dimensionally. Each pixel includes a photodiode PD, a floating diffusion region FD, and transistors Tr1, Tr2, and Tr3. The gates of the transistors Tr1 and Tr2 are connected to the row signal lines 17a and 17b, respectively. The gate of the transistor Tr3 is connected to the floating diffusion FD, and the source of the transistor Tr3 is connected to the column signal line 18 .

[0062] By receiving various driving pulses from the external timing control unit, the load circuit 12, the row selection decoder 13, the column selection decoder 14, the signal processing unit 1...

no. 2 example

[0085] In the second embodiment, the column-sequential readout of pixel signals is suspended by a method different from that described in the first embodiment. Other features are the same as those of the first embodiment, so descriptions thereof are omitted.

[0086] FIG. 10 shows a readout standby operation for suspending column-sequential readout of pixel signals related to the second embodiment of the present invention.

[0087] In a second embodiment, the column select decoder 14 includes a shift register capable of (i) shifting in the forward direction corresponding to the order of the pixel array columns, and (ii) pausing on receipt of a clock pulse shift operation. The shift register shifts in the forward direction when the level of the cyclic scan pulse is low, and the shift operation is suspended when the level of the cyclic scan pulse is high. The level of the cyclic scanning pulse is designed to be: (i) low level during the horizontal readout period except the rea...

no. 3 example

[0096] The third embodiment differs from the first embodiment in that the output of pixel signals to the outside is restricted in the readout standby period. Other features are the same as those of the first embodiment, so descriptions thereof are omitted.

[0097] FIG. 13 shows a readout standby operation for suspending column-sequential readout of pixel signals related to the third embodiment of the present invention.

[0098] In the third embodiment, the pixel signal is output to the outside when the level of the output limit pulse is low, and the pixel signal is not output to the outside when the level of the output limit pulse is high. The level of the output limit pulse is designed to be low level during the horizontal readout period other than the readout standby period, and to be high level during the readout standby period. By designing the output limiting pulse in the above manner, it is possible to limit the output of unnecessary pixel signals during the readout st...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

A solid-state imaging device comprises a pixel array including a plurality of pixels arranged in rows and columns, and a readout unit operable to read out pixel signals of the pixels included in the pixel array row by row. The readout unit (i) reads out pixel signals of a row of pixels in column order of the pixel array during a horizontal readout period, except during a readout-standby period that is within the horizontal readout period, and (ii) suspends reading out the pixel signals of the row of pixels in the column order during the readout-standby period.

Description

technical field [0001] The present invention relates to a solid-state imaging device used in a digital camera or the like, and particularly relates to a technique for suppressing image noise in a MOS type solid-state imaging device. Background technique [0002] Generally, a MOS type solid-state imaging device includes (i) a pixel array including a plurality of pixels arranged in rows and columns and (ii) a signal processing unit that processes and stores pixel signals of a row of pixels included in the pixel array in parallel. During the horizontal blanking period, the signal processing unit processes pixel signals of pixel rows in parallel and stores the processed pixel signals. Then, in the horizontal readout period after the horizontal blanking period, these processed pixel signals are read out from the signal processing unit one by one according to the column order of the pixel array. By repeating the above-described set of operations for each row in a frame, pixel sig...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H04N3/15H04N5/335H04N5/217H04N5/341H04N5/353H04N5/365H04N5/374
Inventor 户谷宽远藤康行
Owner PANASONIC CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap