Scanning chain fault diagnosis method and system

Abstract

The invention discloses a scan chain failure diagnosis method and a system thereof. The method comprises the following steps: a candidate scan unit assembling is made up of scan units in the scan chain of a chip to be tested, and a candidate pair to be tested is selected in the assembling; according to the failure types, a corresponding fixation type failure diagnosis device is established for the candidate pair to be tested; diagnosis vectors are generated for the candidate pair to be tested by utilizing the device, and are stored in the diagnosis vector assembling for processing scan chain failure diagnosis to the chip to be tested. The method also comprises the following steps: all the diagnosis vectors in the diagnosis vector assembling are loaded to the chip to be tested one by one to get failure responses; and according to the failure responses, the scan chain failure diagnosis for the chip to be tested is processed. The failure scan chain is diagnosed in the circumstances without any spending of area and routing by adopting the method, and the traditional scan chain diagnosis flow is not changed, thereby the logic diagnosis cost is reduced.

Description

technical field [0001] The invention relates to the field of diagnosability design of integrated circuits, belongs to a fixed fault location method for logic integrated circuits, and in particular relates to a scanning chain fault diagnosis method and system. Background technique [0002] In recent years, deep submicron and ultra-deep submicron processes have been widely used in the design of integrated circuits to improve performance. At the same time, as the process scale shrinks, the chip defect density gradually increases, and the mass production learning process in each generation process becomes more complicated. Therefore, scan design technology is widely used in the circuit design process to improve the testability (Design-For-Testability, DFT) and diagnosability of the circuit, thereby improving the chip quality and the good rate of chip production. [0003] The design-for-test technique is a widely adopted structured design for testability (DFT) technique. Scan-b...

AI Technical Summary

Problems solved by technology

[0016] However, the existing third type of solutions only diagnose the faults that exist on the scan chain

Once a failure occurs in the scan chain, the subsequent combinatorial logic diagnosis process cannot be carried out, and the failure information in the combinatorial logic cannot be obtained through logic diagnosis; in addition, the third type of solution will bring additional area and wiring overhead to the circuit design , more importantly, the special design for testability will change the traditional industrial process, so this method is rarely applied in the industry

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