Method and device for optimizing chip layout of silicon slice

A chip layout, silicon wafer technology, applied in instrumentation, computing, electrical digital data processing, etc., can solve problems such as unreasonable chip layout

Active Publication Date: 2008-12-03
FOUNDER MICROELECTRONICS INT
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of this, the main purpose of the present invention is to provide a method and device for optimizing chip layout in silicon wafers, so as to solve the problem of unreasonable chip layout in silicon wafers in the prior art

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  • Method and device for optimizing chip layout of silicon slice
  • Method and device for optimizing chip layout of silicon slice
  • Method and device for optimizing chip layout of silicon slice

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Embodiment Construction

[0027] The technical solutions of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

[0028] The present invention provides a method for optimizing chip layout in a silicon chip. According to the actual situation, the layout parameters such as Edge Exclude, FlatEdge Height and FlatEdge Length are set when drawing WaferMap, and the Wafer Map drawn is fine-tuned through the set Offset, which can make the drawing The resulting Wafer Map is closer to the actual silicon wafer, and a more reasonable chip layout in the silicon wafer is obtained.

[0029] A method for optimizing chip layout in a silicon wafer provided by the present invention, such as figure 1 As shown, it mainly includes the following steps:

[0030] Step 101, acquiring layout parameters of the silicon chip, the layout parameters including Edge Exclude, FlatEdge Height and FlatEdge Length of the silicon chip.

[0031] The method for optimi...

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Abstract

The invention discloses a method for chip layout in an optimized silicon chip, which comprises the steps that: the layout parameters of the silicon chip is obtained, comprising the washing edge width, the plain edge height and the large plain edge length of the silicon chip; the exposure field wafer map of the silicon chip is generated according to the obtained layout parameters; the chip layout is carried out to the silicon chip according to the generated wafer map. The invention also discloses a device used for optimizing the chip layout in the silicon chip, the wafer map is determined according to the layout parameters; and fine adjustment is carried out to the wafer map by offset so as to cause the wafer map to be more close to the real silicon chip, and the effective area of the silicon chip can be fully utilized, thus causing the gross die of the effective chips of the layout on the silicon chip to be maximized.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method and a device for optimizing chip layout in a silicon chip. Background technique [0002] With the development of semiconductor technology, as well as the increasing requirements for the miniaturization of electronic devices and circuit integration density in the semiconductor industry, in the process of semiconductor wafer processing, it is usually necessary to integrate as many chips as possible on the silicon wafer, so as to make better use of the silicon wafer area. The so-called wafer refers to the silicon chip used in the production of semiconductor integrated circuits. Since the shape of the silicon chip is circular, it is also called a wafer. Silicon wafers are the most commonly used semiconductor materials. Current silicon wafers include various sizes such as 4 inches (inch), 5 inches, 6 inches, 8 inches and 12 inches, wherein 4 inches, 5 inches, 6 inches...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 闻正锋
Owner FOUNDER MICROELECTRONICS INT
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