Chip, chip interconnection system and method for calibrating chip interconnection

A chip and syndrome technology, applied in the electronic field, can solve problems such as the complexity of chip interconnection verification, and achieve the effect of simple technology and convenient testing

A chip and syndrome technology, applied in the electronic field, can solve problems such as the complexity of chip interconnection verification, and achieve the effect of simple technology and convenient testing

CN101334444AInactive Publication Date: 2008-12-31HUAWEI TECH CO LTD
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  • Chip, chip interconnection system and method for calibrating chip interconnection
  • Chip, chip interconnection system and method for calibrating chip interconnection
  • Chip, chip interconnection system and method for calibrating chip interconnection

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Embodiment Construction

[0017] Embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0018] The invention discloses a chip interconnection system, an embodiment of which is as follows figure 1 As shown, it includes an interconnected front-end chip 100 and a back-end chip 200 , the front-end chip 100 includes a check sequence sending unit 110 , and the back-end chip 200 includes a check sequence receiving unit 210 . Wherein, the check sequence sending unit 110 uses a plurality of single-bit data to generate a shifted check sequence according to a preset check algorithm, and sends the data of the shifted check sequence to the subsequent chip 200 in sequence; the check sequence receives The unit 210 uses the same multiple single-bit data as the check sequence sending unit 110, and generates a shifted comparison sequence according to the same check algorithm as that in the check sequence sending unit 110, and then compares the shifted compar...

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Abstract

The invention discloses an interconnecting system for checking chips, which comprises a pre-chip and a post-chip which are interconnected, the pre-chip comprises a check sequence sending unit, the post-chip comprises a check sequence receiving unit, the check sequence sensing unit uses a plurality of single-bit data for generating a displacement check sequence, the data of the displacement check sequence is sequentially sent to the post-chip; the check sequence receiving unit uses the data in the displacement check sequence for generating a displacement comparison sequence, and the displacement comparison sequence is compared with the received displacement check sequence for obtaining a check result. The invention further discloses an interconnecting method for checking the chips and a chip, the check of the chip interconnection can be realized through the comparison of the check sequence and the comparison sequence, the technology is simple and practicable, and the test is convenient.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a chip, a chip interconnection system and a method for verifying chip interconnection. Background technique [0002] With the development of integrated circuit technology, the integration of electronic devices and product systems is getting higher and higher, and the complexity is also increasing. Therefore, the testing technology for chip components in the circuit system and the connections between chips is also becoming increasingly complex. [0003] In the prior art, verification for chip interconnection is usually performed using a JTAG (Joint Test Action Group, joint test action group) interface or a CRC (Cyclical Redundancy Check, cyclic redundancy check) check code. The former can detect the interconnection of the chip through the JATG standard test interface and cooperate with the emulator, but it cannot detect the timing problem of the chip interface; while the impl...

Claims

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Application Information

Patent Timeline
31 Dec 2008
Publication
CN101334444A
IPC
G01R31/28; G01R31/317
Inventors
汪达生