Methods of patterning self-assembly nano-structure and forming porous dielectric

Abstract

Methods of patterning a self-assembly nano-structure and forming a porous dielectric are disclosed. In one aspect, the method includes providing a hardmask over an underlying layer; predefining an area with a photoresist on the hardmask that is to be protected during the patterning; forming a layer of the copolymer over the hardmask and the photoresist; forming the self-assembly nano-structure from the copolymer; and etching to pattern the self-assembly nano-structure.

Description

technical field [0001] The present invention relates generally to integrated circuit (IC) chip fabrication, and more particularly to methods of patterning self-assembled nanostructures for forming porous dielectrics and methods of forming the porous dielectrics. Background technique [0002] In the integrated circuit (IC) chip manufacturing industry, back-end-of-line (BEOL) interconnects have been the target of improvements to minimize circuit delays. One way to reduce circuit delays is to start with conventional silicon dioxide (SiO 2 ) dielectric (dielectric constant (k) about 3.9) into a dense low-k material (k < 3.0), such as hydrogenated silicon oxycarbide (SiCOH). For further performance improvement, more parasitic capacitance reduction (eg, k<2.5) is required for high-speed circuits. [0003] Reduced parasitic capacitance can be achieved with new porous low-k dielectrics, such as self-assembled nanostructures. However, most porous materials have relatively we...

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Problems solved by technology

Therefore, as shown in FIGS. 6-7, the pattern in the hard mask 14, and thus the porous dielectric 24, can be non-uniform, which reduces the degree of performance improvement.

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