Method for preventing non-volatility memory array from generating bit line interference

Abstract

The invention discloses a method for preventing a non-volatile memory array from producing a bit line interference, the non-volatile memory array comprises a plurality of storage units which comprises gates, source cathodes and drains and are arranged in an array form, the gates of the storage units on each row are all connected with a word line, the source cathodes and the drains of the storage units on each column are respectively connected with a bit line, and the storage units on two adjacent columns share a bit line. When a certain storage unit receives programming, if one bit line of the two bit lines which are connected with other storage units is located on a high electric potential and the other one is located on an impending state, the other storage units are loaded with source cathode bias voltage and substrate bias voltage. Using the method of the invention, the non-volatile memory array can be prevented from producing the bit line interference, thereby increasing the performance of memory devices.

Description

technical field [0001] The invention relates to the erasing and writing technology of data of semiconductor devices, in particular to a method for preventing bit line interference from non-volatile memory arrays. Background technique [0002] Nonvolatile memory (nonvolatile memory) is a commonly used semiconductor device. According to different materials and structures, nonvolatile memory can be divided into many types. Taking nitrogen read-only memory (NROM) as an example, it has such figure 1 The device structure shown includes: a substrate 1, a source 2 and a drain 3 formed in the substrate 1, and a gate 4 formed above the substrate 1, wherein the gate 4 and the substrate 1 There are also three superimposed insulating layers 51, 52, 53 between them, the middle layer 52 is a charge-trapping layer for storing data, and the insulating layers 51, 53 on the upper and lower sides are used to lock the middle Layer 52 charges. Two ends of the charge trapping layer 52 have char...

AI Technical Summary

Problems solved by technology

[0004] When a memory cell on a certain bit line needs to be programmed, it is easy to interfere with adjacent memory cells

Taking the memory cell C11 as an example, it is necessary to add a high potential to the bit line BL2 when programming it, because the memory cells C22 and C11 share the bit line BL2, so the source of C22 also presents a high potential, because the bit line BL3 is suspended Therefore, there will be a potential difference between the source and drain of C22, which will cause the threshold voltage variation DVt of the memory cell C22 to increase, thereby affecting the performance of the memory cell

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