Method for preventing memory array generating bit line interference

A memory array and bit line technology, applied in static memory, read-only memory, information storage, etc., can solve the problems of memory cell interference, increase of threshold voltage variation DVt, and influence on memory cell performance, so as to reduce potential difference, Improving the Effect of Bit Line Disturbance
CN101373636BActive Publication Date: 2010-12-22SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Patents(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2010-12-22

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Abstract

The invention discloses a method for preventing a memory array from generating bit line interference. The memory array consists of a plurality of storage units which are in array management, wherein each storage unit comprises a grid, a source electrode, and a drain electrode. The grids of the storage units in each row are connected to form a straight line. The source electrodes and the drain electrodes of the storage units of each row are connected to a bit line. Two adjacent storage units share a bit line. According to the method, when a certain storage unit is programmed, and if two bit lines connected to the other storage units are in high potential, and one bit line connected thereto is in suspension state or in low potential, a grid bias voltage is loaded to the other storage units.The method of the invention can prevent the nonvolatile memory from generating bit line interference, thereby improving the performance of the memory.
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Description

technical field

[0001] The invention relates to the erasing and writing technology of data of semiconductor devices, in particular to a method for preventing bit line interference from non-volatile memory arrays. Background technique

[0002] Nonvolatile memory (nonvolatile memory) is a commonly used semiconductor device. According to different materials and structures, nonvolatile memory can be divided into many types. Taking nitrogen read-only memory (NROM) as an example, it has such figure 1 The device structure shown includes: a substrate 1, a source 2 and a drain 3 formed in the substrate 1, and a gate 4 formed above the substrate 1, wherein the gate 4 and the substrate 1 There are also three superimposed insulating layers 51, 52, 53 between them, the middle layer 52 is a charge-trapping layer for storing data, and the insulating layers 51, 53 on the upper and lower sides are used to lock the middle Layer 52 charges. Two ends of the charge trapping layer 52 have char...

Claims

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