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Integrated circuit package structure

A packaging structure, integrated circuit technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., can solve the problems of decreased yield, unreliability, open circuit, etc. of electrical connection processing, and achieve the effect of improving reliability and yield

Inactive Publication Date: 2010-08-25
浙江华越芯装电子股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, a disadvantage of this packaging structure is that when the electrical connection is processed, because the contact part of the pin is suspended above the chip carrier, the contact part of the pin cannot be compacted and fixed during processing, and it is easy to float, making the contact of the electrical connection difficult to process. reliable, causing an open circuit
Or even if the elasticity of the pins is used to press the electrical connection points of the pins tightly on the chip carrier, the surface of the electrical connection areas of the pins will be in contact with the chip due to the safe distance between the pins and the chip carrier. The plane of the carrier board produces an oblique angle, which reduces the yield of electrical connection processing

Method used

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Embodiment Construction

[0020] As shown in Fig. 1, Fig. 2 and Fig. 3, the present invention includes a lead frame 10 and an encapsulant 40. A chip carrier 11 is formed in the middle of the lead frame 10, and several pins 12 are arranged around the chip carrier 11. The chip 30 is The way of alloy solder bonding is fixed on the chip carrier 11, the electrical connection point area 13 of the pin 12 is formed above the chip carrier 11, and the pad element 20 is provided between the pin 12 and the chip carrier 11, The pad element 20 is made of a high temperature resistant, hard insulating material. The pad element 20 is placed on the corresponding pin electrical connection point area 13 projection position on the chip carrier 11, and the pin electrical connection point area 13 is connected to the pad element. 20 , and between the pad component 20 and the chip carrier 11 are in contact with no gap.

[0021] As shown in FIG. 4 , the pad component 20 includes a pad base 21 and a pad boss 22 arranged between ...

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Abstract

The invention relates to an integrated circuit package structure which is applied in the technical field of high-power integrated circuit encapsulation. The integrated circuit package structure comprises a lead frame and a packaging colloid. A chip carrier is arranged at the middle of the lead frame and a plurality of pins are arranged around the chip carrier; a chip is fixed on the chip carrier and an electric joint area for the pins is arranged above the chip carrier; and a connection pad element is arranged between the pins and the chip carrier, in the projection of the corresponding electric connection point area on the chip carrier. The electric connection point area and the connection pad element, and the connection pad element and the chip carrier are both in non-clearance contact,thus ensuring the reliability of the contacts on the pins at the time of electric connection process of the products in package so as to improve yield and reliability of the products.

Description

technical field [0001] The invention relates to an integrated circuit package structure, specifically a package structure in which the lead layer is parallel to the chip carrier layer, and the vertical projection of the electrical connection contact area of ​​the lead layer is located in the plane of the chip carrier layer , used in high-power integrated circuit packaging technology. Background technique [0002] With the increasingly widespread application of integrated circuits and the continuous improvement of microelectronic packaging (Packaging) and high-power packaging technologies, a novel high-power integrated circuit packaging method has gradually become more common. Its main feature is that the pins are perpendicular to the top of the chip carrier board, and the vertical projection of the electrical connection point of the pins is located in the plane of the chip carrier board layer. This packaging structure can increase the effective heat conduction area of ​​the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L23/31
CPCH01L2924/0002
Inventor 张永夫林刚强
Owner 浙江华越芯装电子股份有限公司