Nonvolatile semiconductor memory device

A storage device, non-volatile technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, information storage, etc., can solve the problems of unusable reliability, deterioration of charge retention characteristics, and non-negligible charging loss bits, etc., to achieve stability discrete small effects

Inactive Publication Date: 2009-03-25
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when the gate insulating film is thin, the deterioration of the charge retention characteristics may become conspicuous, and the charge loss bit may not be ignored, and the reliability may become unusable.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0060] A nonvolatile semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. figure 1 It is a partial cross-sectional view schematically showing the configuration of the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention.

[0061] figure 1 The non-volatile semiconductor storage device is Nch type, and N+ type source 2 and drain 3 are formed on the surface of P-type semiconductor substrate 1 (also can be P well), and between source 2 and drain 3 A gate electrode 5 is formed on the intermediate semiconductor substrate 1 via a gate insulating film 4 (for example, a silicon oxide film). A part of the gate electrode 5 becomes the non-doped region 10 (such as polysilicon), and the other region of the gate electrode 5 becomes the doped region 9 (such as N+polysilicon). exist figure 1 Among them, the portion of the gate electrode 5 on the drain 3 side serves as the un...

Embodiment 2

[0072] A nonvolatile semiconductor memory device according to Embodiment 2 of the present invention will be described with reference to the drawings. figure 2 It is a partial cross-sectional view schematically showing the configuration of the nonvolatile semiconductor memory device according to Embodiment 2 of the present invention.

[0073] The configuration of the gate electrode 5 in the nonvolatile semiconductor memory device of the second embodiment is different from that of the first embodiment. The gate electrode 5 is composed of a polysilicon layer, a silicide layer 11, The metal layer 12 is formed. A portion of the polysilicon layer on the drain 3 side serves as an undoped region 10 , and a portion of the polysilicon layer on the source 2 side serves as a doped region 9 . In addition, the metal layer 12 may not be included in the gate electrode 5, and only a polysilicon layer and a silicide layer having the doped region 9 and the non-doped region 10 may be laminated...

Embodiment 3

[0077] A nonvolatile semiconductor memory device according to Embodiment 3 of the present invention will be described with reference to the drawings. image 3 It is a partial sectional view schematically showing the configuration of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

[0078] The configuration of the gate electrode 5 in the nonvolatile semiconductor memory device of the third embodiment is different from that of the first embodiment. Portions of the gate electrode 5 on the side of the drain 3 and the side of the source 2 serve as the doped region 9 (N+ polysilicon), and the central part of the gate electrode 5 serves as the non-doped region 10 (polysilicon). Other configurations and actions are the same as those in Embodiment 1. Also, it is also possible to apply the configuration of the gate electrode 5 as in Embodiment 3 to the polysilicon layer ( figure 2 9, 10 of the layer).

[0079] According to Example 3, t...

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PUM

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Abstract

A nonvolatile semiconductor memory device is provided in which stable transistor characteristics with little variation can be obtained, and sufficient threshold voltage and ON current fluctuations can be obtained. A source 2 and a drain 3 formed on a surface of a semiconductor substrate 1, and a gate electrode 5 formed via a gate insulating film 4 on the semiconductor substrate 1 between the source 2 and the drain 3 are provided, and a region of part of the gate electrode 5 forms a non-doped region 10 in which an impurity is not implanted in polysilicon, and another region of the gate electrode 5 forms a doped region 9 in which an impurity is implanted in the polysilicon.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor memory device. Background technique [0002] Storage of security codes in LSI (Large Scale Integration) suitable for digital home appliances and mobile phones, color tone adjustment parameters in LCD (Liquid Crystal Display) drivers, temperature parameters of TCXO (Temperature Compensated Crystal Oscillator) controlled by crystal transmitters, etc. etc., a small-capacity nonvolatile ROM (Read Only Memory) is increasingly required. Most of such nonvolatile ROMs are equipped with other chips such as EEPROM (Electronically Erasable and Programmable Read Only Memory) as SIP (System In Package). Recently, a floating gate (floating gate) type memory that can be formed by a standard CMOS (Complementary Metal Oxide Semiconductor) process without an additional process has been proposed (for example, Patent Document 1, etc.). on volatile ROM. [0003] As a nonvolatile ROM that is formed by a standar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/49H01L27/115G11C16/10G11C16/14G11C16/26
CPCH01L29/66825G11C16/10H01L29/42324H01L21/28273G11C16/0416H01L29/7885H01L29/40114
Inventor 儿玉典昭
Owner NEC ELECTRONICS CORP
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