Transmission stream deplexing hardware construction and implementation method
A technology of hardware structure and implementation method, which is applied in the direction of electrical components, TV, selective content distribution, etc., and can solve problems such as large CPU occupancy rate, limited performance of software demultiplexing speed, and unfavorable CPU performance.
Inactive Publication Date: 2009-06-10
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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The purpose of TS stream demultiplexing is to separate various mixed audio and video streams from TS streams. At present, the usual demultiplexing methods include software demultiplexing, hardware demultiplexing and software and hardware demultiplexing. , the speed of software demultiplexing is limited by the performance of the CPU, and at the same time, it occupies a large share of the CPU, which is not conducive to giving full play to the performance of the CPU; hardware demultiplexing can solve the speed limit of demultiplexing, but it is difficult to flexibly respond to the future development needs
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[0035] The specific implementation of each module is as follows:
[0036] The TS stream signal enters the hardware processing circuit through the SPI interface. There is an input processing logic inside the input part. The logic receives the TS stream packet into Buffer1 according to the timing of the SPI interface. The SPI interface supports two modes of input, one is 188 bytes TS stream packet input, one is 204-byte TS stream packet input, the input timing is as follows Figure 4 and Figure 5shown. The difference between the two modes is that in the first mode, a packet has only 188 bytes, and the DVALID signal is always high; in the second mode, besides the data of 188 bytes, there are 16 bytes of stuffing bytes, The DVALID signal is high during the first 188 bytes and low during the 16 stuff bytes. Each time the input processing logic receives a TS flow packet, it notifies the packet processing part to start packet processing. When the packet processing part is proces...
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The invention describes a hardware structure for a transport stream (TS stream) demultiplexing and a realizing method thereof. A circuit is provided with a software interface control register so as to facilitate adopting a mode of collaboration of software and hardware for demultiplexing the TS stream according with DVB standard. A hardware circuit extracts and stores data with various types in the TS stream in a main memory and notifies a master control CPU so as to make decoding control in the next step. The invention mainly provides the hardware circuit structure and the realizing method so as to meet the requirement of integrating a set top box or a digital television receiving SOC chip. The circuit structure mainly comprises an input part, a packet processing part, an output part and a bus interface part.
Description
technical field [0001] The invention is a hardware structure for demultiplexing transport streams following the DVB standard, and is mainly used in the fields of digital TV decoding chips and digital TV set-top box chips. Background technique [0002] Video images and sounds are coded and compressed to generate respective elementary streams (ES, Elementary Stream). These ES streams and auxiliary data must be combined together to form an actual TV program transmission information stream. The first part of the MPEG2 standard (ISO / IEC13818-1) specifies the multiplexing and demultiplexing methods of multiple programs in detail, and the ES streams of video and audio and auxiliary data are allocated to the multiplexed high-speed binary digital bits according to the required frequency band In each transmission time slot of the stream, one TS stream is formed for transmission. From the time point of view, each ES stream in the TS stream is transmitted in time-sharing and in turn. T...
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IPC IPC(8): H04N7/26H04N21/2368H04N21/434
Inventor 魏春峰邹明洪陈波涛马依迪
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD